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Searched refs:VM_CONTEXT0_PAGE_TABLE_BASE_ADDR (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/radeon/
Dsi_dma.c193 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2)); in si_dma_vm_flush()
Dni_dma.c453 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2)); in cayman_dma_vm_flush()
Dni.c1311 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cayman_pcie_gart_enable()
1331 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), in cayman_pcie_gart_enable()
1368 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2)); in cayman_pcie_gart_disable()
2700 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)); in cayman_vm_flush()
Dcik_sdma.c955 radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2); in cik_dma_vm_flush()
Drv770d.h638 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C macro
Dnid.h166 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C macro
Dsid.h443 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c macro
Dcikd.h567 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c macro
Drv770.c927 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in rv770_pcie_gart_enable()
Dsi.c4310 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in si_pcie_gart_enable()
4331 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), in si_pcie_gart_enable()
4372 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2); in si_pcie_gart_disable()
5078 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2); in si_vm_flush()
Devergreend.h1142 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C macro
Dcik.c5508 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cik_pcie_gart_enable()
5525 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), in cik_pcie_gart_enable()
5601 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2); in cik_pcie_gart_disable()
5747 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2); in cik_vm_flush()
Dr600d.h579 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 macro
Dr600.c1165 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in r600_pcie_gart_enable()
Devergreen.c2542 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in evergreen_pcie_gart_enable()
/drivers/gpu/drm/amd/amdgpu/
Dgmc_v6_0.c409 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); in gmc_v6_0_gart_enable()
430 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, in gmc_v6_0_gart_enable()
Dsi_dma.c479 amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); in si_dma_ring_emit_vm_flush()
Dgfx_v6_0.c1976 amdgpu_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id )); in gfx_v6_0_ring_emit_vm_flush()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h445 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54F macro