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Searched refs:VM_L2_CNTL2 (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgmc_v6_0.c402 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in gmc_v6_0_gart_enable()
503 WREG32(VM_L2_CNTL2, 0); in gmc_v6_0_gart_disable()
Dgmc_v7_0.c517 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v7_0_gart_enable()
518 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
Dgmc_v8_0.c627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v8_0_gart_enable()
628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
/drivers/gpu/drm/radeon/
Drv770.c909 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_enable()
955 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_disable()
986 WREG32(VM_L2_CNTL2, 0); in rv770_agp_enable()
Drv770d.h647 #define VM_L2_CNTL2 0x1404 macro
Dnid.h117 #define VM_L2_CNTL2 0x1404 macro
Dni.c1304 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable()
1383 WREG32(VM_L2_CNTL2, 0); in cayman_pcie_gart_disable()
Dsid.h378 #define VM_L2_CNTL2 0x1404 macro
Dcikd.h498 #define VM_L2_CNTL2 0x1404 macro
Devergreen.c2515 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_enable()
2568 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_disable()
2598 WREG32(VM_L2_CNTL2, 0); in evergreen_agp_enable()
Devergreend.h1155 #define VM_L2_CNTL2 0x1404 macro
Dr600d.h592 #define VM_L2_CNTL2 0x1404 macro
Dr600.c1140 WREG32(VM_L2_CNTL2, 0); in r600_pcie_gart_enable()
1232 WREG32(VM_L2_CNTL2, 0); in r600_agp_enable()
Dsi.c4303 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable()
4389 WREG32(VM_L2_CNTL2, 0); in si_pcie_gart_disable()
Dcik.c5501 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()
5620 WREG32(VM_L2_CNTL2, 0); in cik_pcie_gart_disable()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h380 #define VM_L2_CNTL2 0x501 macro