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Searched refs:VM_L2_CNTL3 (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgmc_v7_0.c521 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); in gmc_v7_0_gart_enable()
522 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); in gmc_v7_0_gart_enable()
523 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); in gmc_v7_0_gart_enable()
Dgmc_v8_0.c631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); in gmc_v8_0_gart_enable()
632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); in gmc_v8_0_gart_enable()
633 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); in gmc_v8_0_gart_enable()
Dgmc_v6_0.c403 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in gmc_v6_0_gart_enable()
504 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in gmc_v6_0_gart_disable()
/drivers/gpu/drm/radeon/
Drv770.c910 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_enable()
956 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_disable()
987 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_agp_enable()
Drv770d.h650 #define VM_L2_CNTL3 0x1408 macro
Dnid.h120 #define VM_L2_CNTL3 0x1408 macro
Dni.c1305 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cayman_pcie_gart_enable()
1384 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cayman_pcie_gart_disable()
Dsid.h385 #define VM_L2_CNTL3 0x1408 macro
Dcikd.h505 #define VM_L2_CNTL3 0x1408 macro
Dr600.c1141 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_pcie_gart_enable()
1193 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_pcie_gart_disable()
1233 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_agp_enable()
Devergreen.c2516 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_enable()
2569 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_disable()
2599 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_agp_enable()
Devergreend.h1158 #define VM_L2_CNTL3 0x1408 macro
Dr600d.h595 #define VM_L2_CNTL3 0x1408 macro
Dsi.c4304 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in si_pcie_gart_enable()
4390 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in si_pcie_gart_disable()
Dcik.c5502 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_enable()
5621 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_disable()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h387 #define VM_L2_CNTL3 0x502 macro