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Searched refs:WR (Results 1 – 10 of 10) sorted by relevance

/drivers/block/paride/
Dbpck.c105 #define WR(r,v) bpck_write_regr(pi,2,r,v) macro
114 case 0: WR(4,0x40); in bpck_write_block()
117 WR(4,0); in bpck_write_block()
120 case 1: WR(4,0x50); in bpck_write_block()
123 WR(4,0x10); in bpck_write_block()
126 case 2: WR(4,0x48); in bpck_write_block()
130 WR(4,8); in bpck_write_block()
133 case 3: WR(4,0x48); in bpck_write_block()
137 WR(4,8); in bpck_write_block()
140 case 4: WR(4,0x48); in bpck_write_block()
[all …]
Depia.c104 #define WR(r,v) epia_write_regr(pi,0,r,v) macro
124 WR(0x86,8); in epia_connect()
175 case 3: if (count > 512) WR(0x84,3); in epia_read_block()
178 w2(4); WR(0x84,0); in epia_read_block()
181 case 4: if (count > 512) WR(0x84,3); in epia_read_block()
184 w2(4); WR(0x84,0); in epia_read_block()
187 case 5: if (count > 512) WR(0x84,3); in epia_read_block()
190 w2(4); WR(0x84,0); in epia_read_block()
215 case 3: if (count < 512) WR(0x84,1); in epia_write_block()
218 if (count < 512) WR(0x84,0); in epia_write_block()
[all …]
Depat.c200 #define WR(r,v) epat_write_regr(pi,2,r,v) macro
224 WR(0x8,0x12);WR(0xc,0x14);WR(0x12,0x10); in epat_connect()
225 WR(0xe,0xf);WR(0xf,4); in epat_connect()
227 WR(0xe,0xd);WR(0xf,0); in epat_connect()
241 WR(8,0x10); WR(0xc,0x14); WR(0xa,0x38); WR(0x12,0x10); in epat_connect()
273 WR(0x13,1); WR(0x13,0); WR(0xa,0x11); in epat_test_proto()
297 WR(0xa,0x38); /* read the version code */ in epat_log_adapter()
/drivers/i2c/busses/
Di2c-au1550.c53 static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v) in WR() function
114 WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR); in do_address()
117 WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC); in do_address()
133 WR(adap, PSC_SMBTXRX, addr); in do_address()
134 WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS); in do_address()
178 WR(adap, PSC_SMBTXRX, 0); in i2c_read()
186 WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP); in i2c_read()
206 WR(adap, PSC_SMBTXRX, data); in i2c_write()
215 WR(adap, PSC_SMBTXRX, data); in i2c_write()
228 WR(adap, PSC_CTRL, PSC_CTRL_ENABLE); in au1550_xfer()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
79 WR = ram->next->bios.timing_10_WR; in nvkm_gddr3_calc()
87 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_gddr3_calc()
103 WR = ramxlat(ramgddr3_wr_lo, WR); in nvkm_gddr3_calc()
104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0) in nvkm_gddr3_calc()
115 ram->mr[1] |= (WR & 0x03) << 4; in nvkm_gddr3_calc()
116 ram->mr[1] |= (WR & 0x04) << 5; in nvkm_gddr3_calc()
Dsddr2.c62 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
67 WR = ram->next->bios.timing_10_WR; in nvkm_sddr2_calc()
73 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_sddr2_calc()
86 WR = ramxlat(ramddr2_wr, WR); in nvkm_sddr2_calc()
87 if (CL < 0 || WR < 0) in nvkm_sddr2_calc()
91 ram->mr[0] |= (WR & 0x07) << 9; in nvkm_sddr2_calc()
Dsddr3.c71 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
83 WR = ram->next->bios.timing_10_WR; in nvkm_sddr3_calc()
89 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_sddr3_calc()
101 WR = ramxlat(ramddr3_wr, WR); in nvkm_sddr3_calc()
102 if (CL < 0 || CWL < 0 || WR < 0) in nvkm_sddr3_calc()
106 ram->mr[0] |= (WR & 0x07) << 9; in nvkm_sddr3_calc()
Dgddr5.c38 int WL, CL, WR, at[2], dt, ds; in nvkm_gddr5_calc() local
60 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_gddr5_calc()
70 if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35) in nvkm_gddr5_calc()
73 WR -= 4; in nvkm_gddr5_calc()
76 ram->mr[0] |= (WR & 0x0f) << 8; in nvkm_gddr5_calc()
118 ram->mr[8] |= (WR & 0x10) >> 3; in nvkm_gddr5_calc()
Dramnv50.c110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
177 T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL); in nv50_ram_timing_read()
Dramgt215.c375 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in gt215_ram_timing_calc()