Searched refs:Write (Results 1 – 13 of 13) sorted by relevance
2567 } Write; member2588 } Write; member2640 InboundDoorBellRegister.Write.HardwareMailboxNewCommand = true; in DAC960_GEM_HardwareMailboxNewCommand()2650 InboundDoorBellRegister.Write.AcknowledgeHardwareMailboxStatus = true; in DAC960_GEM_AcknowledgeHardwareMailboxStatus()2660 InboundDoorBellRegister.Write.GenerateInterrupt = true; in DAC960_GEM_GenerateInterrupt()2670 InboundDoorBellRegister.Write.ControllerReset = true; in DAC960_GEM_ControllerReset()2680 InboundDoorBellRegister.Write.MemoryMailboxNewCommand = true; in DAC960_GEM_MemoryMailboxNewCommand()2710 OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true; in DAC960_GEM_AcknowledgeHardwareMailboxInterrupt()2720 OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true; in DAC960_GEM_AcknowledgeMemoryMailboxInterrupt()2730 OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true; in DAC960_GEM_AcknowledgeInterrupt()[all …]
43 static void Write##name##_IO(void *p, u8 off, u8 val) { \62 static void Write##name##_IND(void *p, u8 off, u8 val) { \83 static void Write##name##_MIO(void *p, u8 off, u8 val) { \100 dest.write_reg = &Write##name##_##typ; \
23 COR (Clear-On-Read) or W1C (Write-1-to-Clear) mode.
53 Write the value associated with on sensor event detectors. E.g.
180 echo "1 0xa060 0x12" > regrdwr : Write the MAC register182 : Write 0x80000000 to MAC register
18 generate an interrupt using an inbound Memory Write on its
236 bool "Write support for NFTL"288 Write support is only lightly tested, therefore this driver
3167 * Data FIFO Write Address3240 * Read/Write byte port into the data FIFO. The read and write3267 * Write Bias Control3296 * Write Bias Calculator3589 * 2's complement to bit value conversion. Write the 2's complement value3593 * Write 0x60
144 * SCSI Control Signal Write Register (p. 3-16).215 * Read/Write latches used to transfer data on the SCSI bus during
243 Write the number of the interface that you wish to
122 which trigger the DRAM ECC Read and Write respectively.
150 Note that jumper 3 ("Write Enable Drive A") must be set
1315 #define Write 6 macro