Searched refs:XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (Results 1 – 2 of 2) sorted by relevance
38 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) macro580 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; in pcie_phy_power_on()604 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; in pcie_phy_power_off()
65 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) macro1110 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; in tegra124_pcie_phy_power_on()1143 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; in tegra124_pcie_phy_power_off()