Home
last modified time | relevance | path

Searched refs:YCLK_POST_DIV_MASK (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/radeon/
Drv740d.h53 #define YCLK_POST_DIV_MASK (3 << 17) macro
Drv740_dpm.c213 YCLK_POST_DIV_MASK | in rv740_populate_mclk_value()
230 YCLK_POST_DIV_MASK | in rv740_populate_mclk_value()
Drv770d.h126 #define YCLK_POST_DIV_MASK (3 << 17) macro
Dnid.h568 #define YCLK_POST_DIV_MASK (3 << 17) macro
Dcypress_dpm.c515 YCLK_POST_DIV_MASK | in cypress_populate_mclk_value()
532 YCLK_POST_DIV_MASK | in cypress_populate_mclk_value()
Dsid.h625 #define YCLK_POST_DIV_MASK (7 << 0) macro
Dcikd.h750 #define YCLK_POST_DIV_MASK (7 << 0) macro
Drv770_dpm.c429 YCLK_POST_DIV_MASK | in rv770_populate_mclk_value()
457 YCLK_POST_DIV_MASK | in rv770_populate_mclk_value()
Devergreend.h106 #define YCLK_POST_DIV_MASK (3 << 17) macro
Dni_dpm.c2196 YCLK_POST_DIV_MASK | in ni_populate_mclk_value()
2213 YCLK_POST_DIV_MASK | in ni_populate_mclk_value()
Dci_dpm.c2800 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; in ci_calculate_mclk_params()
2804 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); in ci_calculate_mclk_params()
Dsi_dpm.c4959 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; in si_populate_mclk_value()
4963 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); in si_populate_mclk_value()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h627 #define YCLK_POST_DIV_MASK (7 << 0) macro
/drivers/gpu/drm/amd/amdgpu/
Dsi_dpm.c5439 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; in si_populate_mclk_value()
5443 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); in si_populate_mclk_value()