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Searched refs:__offset_WB (Results 1 – 1 of 1) sorted by relevance

/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5.xml.h1373 static inline uint32_t __offset_WB(uint32_t idx) in __offset_WB() function
1386 static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } in REG_MDP5_WB()
1388 static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } in REG_MDP5_WB_DST_FORMAT()
1455 static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); } in REG_MDP5_WB_DST_OP_MODE()
1509 static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(… in REG_MDP5_WB_DST_PACK_PATTERN()
1535 static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); } in REG_MDP5_WB_DST0_ADDR()
1537 static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); } in REG_MDP5_WB_DST1_ADDR()
1539 static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); } in REG_MDP5_WB_DST2_ADDR()
1541 static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); } in REG_MDP5_WB_DST3_ADDR()
1543 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0);… in REG_MDP5_WB_DST_YSTRIDE0()
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