| /drivers/clk/sunxi-ng/ |
| D | ccu_div.h | 50 #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \ argument
54 .flags = _flags, \
61 #define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \ argument
65 .flags = _flags, \
69 #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \ argument
70 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
88 _table, _gate, _flags) \ argument
98 _flags), \
105 _table, _flags) \ argument
108 _flags)
[all …]
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| D | ccu_common.h | 27 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
29 .flags = _flags, \
36 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
38 .flags = _flags, \
46 _div, _mult, _flags) \ argument
53 _flags), \
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| D | ccu_mux.h | 48 _flags) \ argument
57 _flags), \
62 _shift, _width, _gate, _flags) \ argument
65 _flags)
68 _flags) \ argument
70 _reg, _shift, _width, 0, _flags)
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| D | ccu_mp.h | 42 _gate, _flags) \ argument
53 _flags), \
61 _flags) \ argument
66 0, _flags)
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| D | ccu_nm.h | 45 _gate, _lock, _flags) \ argument
60 _flags), \
67 _gate, _lock, _flags) \ argument
78 _flags), \
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| D | ccu_nkm.h | 45 _gate, _lock, _flags) \ argument
58 _flags), \
66 _gate, _lock, _flags) \ argument
78 _flags), \
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| D | ccu_phase.h | 28 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ argument
37 _flags), \
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| D | ccu_gate.h | 27 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
35 _flags), \
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| D | ccu_mult.h | 28 _flags) \ argument
37 _flags), \
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| D | ccu_nk.h | 45 _flags) \ argument
58 _flags), \
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| D | ccu_nkmp.h | 45 _gate, _lock, _flags) \ argument
58 _flags), \
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| /drivers/net/wireless/ath/ath5k/ |
| D | ath5k.h | 112 #define AR5K_REG_SM(_val, _flags) \ argument
113 (((_val) << _flags##_S) & (_flags))
116 #define AR5K_REG_MS(_val, _flags) \ argument
117 (((_val) & (_flags)) >> _flags##_S)
124 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ argument
125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
126 (((_val) << _flags##_S) & (_flags)), _reg)
128 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ argument
130 (_mask)) | (_flags), _reg)
132 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ argument
[all …]
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| /drivers/clk/zte/ |
| D | clk.h | 17 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
19 .flags = _flags, \
26 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
28 .flags = _flags, \
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| /drivers/scsi/bfa/ |
| D | bfad_im.h | 125 unsigned long _flags; \
126 spin_lock_irqsave(&(_drv)->bfad_aen_spinlock, _flags); \
130 spin_unlock_irqrestore(&(_drv)->bfad_aen_spinlock, _flags); \
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| /drivers/net/wireless/st/cw1200/ |
| D | main.c | 63 #define RATETAB_ENT(_rate, _rateid, _flags) \ argument
67 .flags = (_flags), \
104 #define CHAN2G(_channel, _freq, _flags) { \ argument
108 .flags = (_flags), \
113 #define CHAN5G(_channel, _flags) { \ argument
117 .flags = (_flags), \
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| /drivers/net/wireless/ath/ath9k/ |
| D | common-init.c | 95 #define RATE(_bitrate, _hw_rate, _flags) { \ argument
97 .flags = (_flags), \
99 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
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| /drivers/clk/nxp/ |
| D | clk-lpc32xx.c | 193 #define LPC32XX_CLK_DEFINE(_idx, _name, _flags, ...) \ argument
196 .flags = _flags, \
1087 #define LPC32XX_DEFINE_FIXED(_idx, _rate, _flags) \ argument
1093 .flags = (_flags), \
1114 #define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \ argument
1119 .ops = (_flags & CLK_MUX_READ_ONLY ? \
1128 .flags = (_flags), \
1135 #define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \ argument
1147 .flags = (_flags), \
1154 #define LPC32XX_DEFINE_GATE(_idx, _reg, _bit, _flags) \ argument
[all …]
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| /drivers/tty/serial/8250/ |
| D | 8250.h | 97 #define SERIAL8250_PORT_FLAGS(_base, _irq, _flags) \ argument
103 .flags = UPF_BOOT_AUTOCONF | (_flags), \
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| /drivers/clk/mediatek/ |
| D | clk-mtk.h | 90 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) { \ argument
101 .flags = _flags, \
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| D | clk-mt8173.c | 1010 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
1018 .flags = _flags, \
1030 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
1033 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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| D | clk-mt8135.c | 604 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg,… argument
610 .flags = _flags, \
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| /drivers/mtd/spi-nor/ |
| D | spi-nor.c | 749 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ argument
761 .flags = (_flags),
763 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ argument
776 .flags = (_flags),
778 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ argument
783 .flags = (_flags),
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| /drivers/clk/tegra/ |
| D | clk-tegra-periph.c | 235 _clk_num, _gate_flags, _clk_id, _flags) \ argument
242 .flags = _flags \
245 #define DIV8(_name, _parent_name, _offset, _clk_id, _flags) \ argument
254 .flags = _flags, \
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| D | clk.h | 644 _flags, _lock) \ argument
658 .flags = _flags \
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| /drivers/video/console/ |
| D | sticore.c | 1098 unsigned long _flags = STI_PTR(flags); in sti_call() local
1106 if (WARN_ONCE(_flags>>32 || _inptr>>32 || _outptr>>32 || _glob_cfg>>32, in sti_call()
1111 ret = pdc_sti_call(func, _flags, _inptr, _outptr, _glob_cfg); in sti_call()
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