| /drivers/clk/sunxi-ng/ |
| D | ccu_div.h | 88 _table, _gate, _flags) \ argument
92 .enable = _gate, \
115 _gate, _flags) \ argument
117 .enable = _gate, \
131 _gate, _flags) \ argument
136 _gate, _flags)
149 _mshift, _mwidth, _gate, \ argument
152 .enable = _gate, \
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| D | ccu_nm.h | 45 _gate, _lock, _flags) \ argument
47 .enable = _gate, \
67 _gate, _lock, _flags) \ argument
69 .enable = _gate, \
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| D | ccu_nkm.h | 45 _gate, _lock, _flags) \ argument
47 .enable = _gate, \
66 _gate, _lock, _flags) \ argument
68 .enable = _gate, \
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| D | ccu_mux.h | 47 _reg, _shift, _width, _gate, \ argument
50 .enable = _gate, \
62 _shift, _width, _gate, _flags) \ argument
64 _reg, _shift, _width, _gate, \
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| D | ccu_gate.h | 27 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
29 .enable = _gate, \
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| D | ccu_mult.h | 27 _mshift, _mwidth, _gate, _lock, \ argument
30 .enable = _gate, \
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| D | ccu_nk.h | 44 _gate, _lock, _postdiv, \ argument
47 .enable = _gate, \
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| D | ccu_nkmp.h | 45 _gate, _lock, _flags) \ argument
47 .enable = _gate, \
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| D | ccu_mp.h | 42 _gate, _flags) \ argument
44 .enable = _gate, \
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| /drivers/clk/mediatek/ |
| D | clk-mtk.h | 90 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) { \ argument
97 .gate_shift = _gate, \
108 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
109 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, CLK_SET_RATE_PARENT)
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| /drivers/clk/nxp/ |
| D | clk-lpc32xx.c | 1211 #define LPC32XX_DEFINE_COMPOSITE(_idx, _mux, _div, _gate) \ argument
1220 .gate = (CLK_PREFIX(_gate) == LPC32XX_CLK__NULL ? NULL :\
1221 &clk_hw_proto[CLK_PREFIX(_gate)].hw0), \
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