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/drivers/clk/mvebu/
Darmada-37xx-periph.c84 #define PERIPH_GATE(_name, _bit) \ argument
85 struct clk_gate gate_##_name = { \
93 #define PERIPH_MUX(_name, _shift) \ argument
94 struct clk_mux mux_##_name = { \
103 #define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \ argument
104 struct clk_double_div rate_##_name = { \
114 #define PERIPH_DIV(_name, _reg, _shift, _table) \ argument
115 struct clk_divider rate_##_name = { \
124 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
125 static PERIPH_GATE(_name, _bit); \
[all …]
/drivers/regulator/
Dmc13xxx.h59 #define MC13xxx_DEFINE(prefix, _name, _reg, _vsel_reg, _voltages, _ops) \ argument
60 [prefix ## _name] = { \
62 .name = #_name, \
67 .id = prefix ## _name, \
71 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
73 .vsel_shift = prefix ## _vsel_reg ## _ ## _name ## VSEL,\
74 .vsel_mask = prefix ## _vsel_reg ## _ ## _name ## VSEL_M,\
77 #define MC13xxx_FIXED_DEFINE(prefix, _name, _reg, _voltages, _ops) \ argument
78 [prefix ## _name] = { \
80 .name = #_name, \
[all …]
Dpfuze100-regulator.c163 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \ argument
164 [_chip ## _ ## _name] = { \
166 .name = #_name, \
170 .id = _chip ## _ ## _name, \
178 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \ argument
179 [_chip ## _ ## _name] = { \
181 .name = #_name,\
185 .id = _chip ## _ ## _name, \
196 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \ argument
197 [_chip ## _ ## _name] = { \
[all …]
/drivers/firmware/
Ddcdbas.h57 #define DCDBAS_DEV_ATTR_RW(_name) \ argument
58 DEVICE_ATTR(_name,0600,_name##_show,_name##_store);
60 #define DCDBAS_DEV_ATTR_RO(_name) \ argument
61 DEVICE_ATTR(_name,0400,_name##_show,NULL);
63 #define DCDBAS_DEV_ATTR_WO(_name) \ argument
64 DEVICE_ATTR(_name,0200,NULL,_name##_store);
66 #define DCDBAS_BIN_ATTR_RW(_name) \ argument
67 struct bin_attribute bin_attr_##_name = { \
68 .attr = { .name = __stringify(_name), \
70 .read = _name##_read, \
[all …]
/drivers/clk/zte/
Dclk.h17 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
20 .name = _name, \
26 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
29 .name = _name, \
58 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
65 .hw.init = CLK_HW_INIT(_name, _parent, &zx_pll_ops, \
69 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
70 ZX_PLL(_name, _parent, _reg, _table, 0, 30)
77 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
84 .hw.init = CLK_HW_INIT(_name, \
[all …]
/drivers/clk/renesas/
Drenesas-cpg-mssr.h46 #define DEF_TYPE(_name, _id, _type...) \ argument
47 { .name = _name, .id = _id, .type = _type }
48 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
49 DEF_TYPE(_name, _id, _type, .parent = _parent)
51 #define DEF_INPUT(_name, _id) \ argument
52 DEF_TYPE(_name, _id, CLK_TYPE_IN)
53 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
55 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
56 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
[all …]
/drivers/s390/scsi/
Dzfcp_sysfs.c15 #define ZFCP_DEV_ATTR(_feat, _name, _mode, _show, _store) \ argument
16 struct device_attribute dev_attr_##_feat##_##_name = __ATTR(_name, _mode,\
18 #define ZFCP_DEFINE_ATTR(_feat_def, _feat, _name, _format, _value) \ argument
19 static ssize_t zfcp_sysfs_##_feat##_##_name##_show(struct device *dev, \
27 static ZFCP_DEV_ATTR(_feat, _name, S_IRUGO, \
28 zfcp_sysfs_##_feat##_##_name##_show, NULL);
30 #define ZFCP_DEFINE_ATTR_CONST(_feat, _name, _format, _value) \ argument
31 static ssize_t zfcp_sysfs_##_feat##_##_name##_show(struct device *dev, \
37 static ZFCP_DEV_ATTR(_feat, _name, S_IRUGO, \
38 zfcp_sysfs_##_feat##_##_name##_show, NULL);
[all …]
/drivers/clk/pistachio/
Dclk.h22 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
27 .name = _name, \
42 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
47 .name = _name, \
62 #define DIV(_id, _name, _pname, _reg, _width) \ argument
68 .name = _name, \
72 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
78 .name = _name, \
89 #define FIXED_FACTOR(_id, _name, _pname, _div) \ argument
93 .name = _name, \
[all …]
/drivers/clk/sunxi-ng/
Dccu_div.h86 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
95 .hw.init = CLK_HW_INIT(_name, \
103 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
106 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
110 #define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \ argument
122 .hw.init = CLK_HW_INIT_PARENTS(_name, \
129 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
132 SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
138 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
141 SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
[all …]
Dccu_common.h27 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
30 .name = _name, \
36 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
39 .name = _name, \
45 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ argument
50 .hw.init = CLK_HW_INIT(_name, \
Dccu_mux.h46 #define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \ argument
54 .hw.init = CLK_HW_INIT_PARENTS(_name, \
61 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
63 SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
67 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
69 SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
/drivers/input/mouse/
Dtrackpoint.c145 #define TRACKPOINT_INT_ATTR(_name, _command, _default) \ argument
146 static struct trackpoint_attr_data trackpoint_attr_##_name = { \
147 .field_offset = offsetof(struct trackpoint_data, _name), \
151 PSMOUSE_DEFINE_ATTR(_name, S_IWUSR | S_IRUGO, \
152 &trackpoint_attr_##_name, \
183 #define TRACKPOINT_BIT_ATTR(_name, _command, _mask, _inv, _default) \ argument
184 static struct trackpoint_attr_data trackpoint_attr_##_name = { \
186 _name), \
192 PSMOUSE_DEFINE_ATTR(_name, S_IWUSR | S_IRUGO, \
193 &trackpoint_attr_##_name, \
[all …]
Dpsmouse.h137 #define __PSMOUSE_DEFINE_ATTR_VAR(_name, _mode, _data, _show, _set, _protect) \ argument
138 static struct psmouse_attribute psmouse_attr_##_name = { \
141 .name = __stringify(_name), \
153 #define __PSMOUSE_DEFINE_ATTR(_name, _mode, _data, _show, _set, _protect) \ argument
156 __PSMOUSE_DEFINE_ATTR_VAR(_name, _mode, _data, _show, _set, _protect)
158 #define PSMOUSE_DEFINE_ATTR(_name, _mode, _data, _show, _set) \ argument
159 __PSMOUSE_DEFINE_ATTR(_name, _mode, _data, _show, _set, true)
161 #define PSMOUSE_DEFINE_RO_ATTR(_name, _mode, _data, _show) \ argument
163 __PSMOUSE_DEFINE_ATTR_VAR(_name, _mode, _data, _show, NULL, true)
165 #define PSMOUSE_DEFINE_WO_ATTR(_name, _mode, _data, _set) \ argument
[all …]
/drivers/pinctrl/mvebu/
Dpinctrl-mvebu.h116 #define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \ argument
118 .name = _name, \
128 #define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func) \ argument
130 .name = _name, \
140 #define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
143 .name = _name, \
150 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
151 _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
153 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
154 _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
[all …]
/drivers/clk/tegra/
Dclk-tegra-audio.c46 #define SYNC(_name) \ argument
48 .name = #_name,\
51 .clk_id = tegra_clk_ ## _name,\
62 #define AUDIO(_name, _offset) \ argument
64 .gate_name = #_name,\
65 .mux_name = #_name"_mux",\
67 .gate_clk_id = tegra_clk_ ## _name,\
68 .mux_clk_id = tegra_clk_ ## _name ## _mux,\
81 #define AUDIO2X(_name, _num, _offset) \ argument
83 .parent = #_name,\
[all …]
Dclk-tegra-periph.c144 #define MUX(_name, _parents, _offset, \ argument
146 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
151 #define MUX_FLAGS(_name, _parents, _offset,\ argument
153 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
158 #define MUX8(_name, _parents, _offset, \ argument
160 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
165 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
166 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
171 #define INT(_name, _parents, _offset, \ argument
173 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
[all …]
/drivers/cpuidle/
Dsysfs.c168 #define define_one_ro(_name, show) \ argument
169 static struct cpuidle_attr attr_##_name = __ATTR(_name, 0444, show, NULL)
170 #define define_one_rw(_name, show, store) \ argument
171 static struct cpuidle_attr attr_##_name = __ATTR(_name, 0644, show, store)
245 #define define_one_state_ro(_name, show) \ argument
246 static struct cpuidle_state_attr attr_##_name = __ATTR(_name, 0444, show, NULL)
248 #define define_one_state_rw(_name, show, store) \ argument
249 static struct cpuidle_state_attr attr_##_name = __ATTR(_name, 0644, show, store)
251 #define define_show_state_function(_name) \ argument
252 static ssize_t show_state_##_name(struct cpuidle_state *state, \
[all …]
/drivers/clk/mediatek/
Dclk-mtk.h36 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
38 .name = _name, \
54 #define FACTOR(_id, _name, _parent, _mult, _div) { \ argument
56 .name = _name, \
90 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) { \ argument
92 .name = _name, \
108 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
109 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, CLK_SET_RATE_PARENT)
111 #define MUX(_id, _name, _parents, _reg, _shift, _width) { \ argument
113 .name = _name, \
[all …]
Dclk-mt8173.c610 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
612 .name = _name, \
649 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
651 .name = _name, \
658 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
660 .name = _name, \
725 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
727 .name = _name, \
756 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
758 .name = _name, \
[all …]
/drivers/cpufreq/
Dcpufreq_governor.h73 #define gov_attr_ro(_name) \ argument
74 static struct governor_attr _name = \
75 __ATTR(_name, 0444, show_##_name, NULL)
77 #define gov_attr_rw(_name) \ argument
78 static struct governor_attr _name = \
79 __ATTR(_name, 0644, show_##_name, store_##_name)
/drivers/md/
Ddm-sysfs.c18 #define DM_ATTR_RO(_name) \ argument
19 struct dm_sysfs_attr dm_attr_##_name = \
20 __ATTR(_name, S_IRUGO, dm_attr_##_name##_show, NULL)
43 #define DM_ATTR_RW(_name) \ argument
44 struct dm_sysfs_attr dm_attr_##_name = \
45 __ATTR(_name, S_IRUGO | S_IWUSR, dm_attr_##_name##_show, dm_attr_##_name##_store)
/drivers/media/i2c/smiapp/
Dsmiapp.h94 #define SMIAPP_IDENT_FQ(manufacturer, model, rev, fl, _name, _quirk) \ argument
99 .name = _name, \
102 #define SMIAPP_IDENT_LQ(manufacturer, model, rev, _name, _quirk) \ argument
107 .name = _name, \
110 #define SMIAPP_IDENT_L(manufacturer, model, rev, _name) \ argument
115 .name = _name, }
117 #define SMIAPP_IDENT_Q(manufacturer, model, rev, _name, _quirk) \ argument
122 .name = _name, \
125 #define SMIAPP_IDENT(manufacturer, model, rev, _name) \ argument
130 .name = _name, }
/drivers/mfd/
Dlm3533-ctrlbank.c96 #define lm3533_ctrlbank_set(_name, _NAME) \ argument
97 int lm3533_ctrlbank_set_##_name(struct lm3533_ctrlbank *cb, u8 val) \
108 dev_err(cb->dev, "failed to set " #_name "\n"); \
112 EXPORT_SYMBOL_GPL(lm3533_ctrlbank_set_##_name);
114 #define lm3533_ctrlbank_get(_name, _NAME) \ argument
115 int lm3533_ctrlbank_get_##_name(struct lm3533_ctrlbank *cb, u8 *val) \
123 dev_err(cb->dev, "failed to get " #_name "\n"); \
127 EXPORT_SYMBOL_GPL(lm3533_ctrlbank_get_##_name);
/drivers/usb/atm/
Dcxacru.c213 #define CXACRU__ATTR_INIT(_name) \ argument
214 static DEVICE_ATTR(_name, S_IRUGO, cxacru_sysfs_show_##_name, NULL)
216 #define CXACRU_CMD_INIT(_name) \ argument
217 static DEVICE_ATTR(_name, S_IWUSR | S_IRUGO, \
218 cxacru_sysfs_show_##_name, cxacru_sysfs_store_##_name)
220 #define CXACRU_SET_INIT(_name) \ argument
221 static DEVICE_ATTR(_name, S_IWUSR, \
222 NULL, cxacru_sysfs_store_##_name)
224 #define CXACRU_ATTR_INIT(_value, _type, _name) \ argument
225 static ssize_t cxacru_sysfs_show_##_name(struct device *dev, \
[all …]
/drivers/iio/health/
Dafe440x.h125 #define AFE440X_TABLE_ATTR(_name, _table) \ argument
126 static ssize_t _name ## _show(struct device *dev, \
141 static DEVICE_ATTR_RO(_name)
153 #define AFE440X_ATTR(_name, _field, _table) \ argument
154 struct afe440x_attr afe440x_attr_##_name = { \
155 .dev_attr = __ATTR(_name, (S_IRUGO | S_IWUSR), \

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