| /drivers/gpu/drm/radeon/ |
| D | dce3_1_afmt.c | 171 const struct radeon_hdmi_acr *acr) in dce3_2_hdmi_update_acr() argument
181 HDMI0_ACR_CTS_32(acr->cts_32khz), in dce3_2_hdmi_update_acr()
184 HDMI0_ACR_N_32(acr->n_32khz), in dce3_2_hdmi_update_acr()
188 HDMI0_ACR_CTS_44(acr->cts_44_1khz), in dce3_2_hdmi_update_acr()
191 HDMI0_ACR_N_44(acr->n_44_1khz), in dce3_2_hdmi_update_acr()
195 HDMI0_ACR_CTS_48(acr->cts_48khz), in dce3_2_hdmi_update_acr()
198 HDMI0_ACR_N_48(acr->n_48khz), in dce3_2_hdmi_update_acr()
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| D | evergreen_hdmi.c | 68 const struct radeon_hdmi_acr *acr) in evergreen_hdmi_update_acr() argument
87 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); in evergreen_hdmi_update_acr()
88 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); in evergreen_hdmi_update_acr()
90 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); in evergreen_hdmi_update_acr()
91 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); in evergreen_hdmi_update_acr()
93 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); in evergreen_hdmi_update_acr()
94 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); in evergreen_hdmi_update_acr()
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| D | r600_hdmi.c | 178 const struct radeon_hdmi_acr *acr) in r600_hdmi_update_acr() argument
193 HDMI0_ACR_CTS_32(acr->cts_32khz), in r600_hdmi_update_acr()
196 HDMI0_ACR_N_32(acr->n_32khz), in r600_hdmi_update_acr()
200 HDMI0_ACR_CTS_44(acr->cts_44_1khz), in r600_hdmi_update_acr()
203 HDMI0_ACR_N_44(acr->n_44_1khz), in r600_hdmi_update_acr()
207 HDMI0_ACR_CTS_48(acr->cts_48khz), in r600_hdmi_update_acr()
210 HDMI0_ACR_N_48(acr->n_48khz), in r600_hdmi_update_acr()
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| D | radeon_audio.c | 83 const struct radeon_hdmi_acr *acr);
85 const struct radeon_hdmi_acr *acr);
87 const struct radeon_hdmi_acr *acr);
628 const struct radeon_hdmi_acr *acr = radeon_audio_acr(clock); in radeon_audio_update_acr() local
636 radeon_encoder->audio->update_acr(encoder, dig->afmt->offset, acr); in radeon_audio_update_acr()
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| D | radeon_audio.h | 57 const struct radeon_hdmi_acr *acr);
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| /drivers/power/supply/ |
| D | ds2760_battery.c | 236 unsigned char acr[2]; in ds2760_battery_set_current_accum() local
242 acr[0] = acr_val >> 8; in ds2760_battery_set_current_accum()
243 acr[1] = acr_val & 0xff; in ds2760_battery_set_current_accum()
245 if (w1_ds2760_write(di->w1_dev, acr, DS2760_CURRENT_ACCUM_MSB, 2) < 2) in ds2760_battery_set_current_accum()
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| /drivers/tty/serial/ |
| D | sunsu.c | 89 unsigned char acr; member
179 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
182 serial_icr_write(up, UART_ACR, up->acr);
276 up->acr |= UART_ACR_TXDIS; in sunsu_stop_tx()
277 serial_icr_write(up, UART_ACR, up->acr); in sunsu_stop_tx()
294 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { in sunsu_start_tx()
295 up->acr &= ~UART_ACR_TXDIS; in sunsu_start_tx()
296 serial_icr_write(up, UART_ACR, up->acr); in sunsu_start_tx()
627 up->acr = 0; in sunsu_startup()
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| D | sccnxp.c | 249 u8 acr; member
289 u8 i, acr = 0, csr = 0, mr0 = 0; in sccnxp_set_baud() local
298 acr = baud_std[i].acr; in sccnxp_set_baud()
313 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); in sccnxp_set_baud()
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| /drivers/ipack/devices/ |
| D | scc2698.h | 73 u8 d4, acr; /* Auxiliary control register of block */ member
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| D | ipoctal.c | 341 iowrite8(ACR_BRG_SET2, &block_regs[i].w.acr); in ipoctal_inst_slot()
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| /drivers/tty/serial/8250/ |
| D | 8250_port.c | 508 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); in serial_icr_read()
511 serial_icr_write(up, UART_ACR, up->acr); in serial_icr_read()
870 up->acr = 0; in autoconfig_has_efr()
1498 up->acr |= UART_ACR_TXDIS; in serial8250_stop_tx()
1499 serial_icr_write(up, UART_ACR, up->acr); in serial8250_stop_tx()
1528 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { in __start_tx()
1529 up->acr &= ~UART_ACR_TXDIS; in __start_tx()
1530 serial_icr_write(up, UART_ACR, up->acr); in __start_tx()
2104 up->acr = 0; in serial8250_do_startup()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | dce_v8_0.c | 1679 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); in dce_v8_0_afmt_update_ACR() local
1684 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT)); in dce_v8_0_afmt_update_ACR()
1685 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz); in dce_v8_0_afmt_update_ACR()
1687 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT)); in dce_v8_0_afmt_update_ACR()
1688 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz); in dce_v8_0_afmt_update_ACR()
1690 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT)); in dce_v8_0_afmt_update_ACR()
1691 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz); in dce_v8_0_afmt_update_ACR()
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| D | dce_v11_0.c | 1711 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); in dce_v11_0_afmt_update_ACR() local
1717 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); in dce_v11_0_afmt_update_ACR()
1720 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v11_0_afmt_update_ACR()
1724 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); in dce_v11_0_afmt_update_ACR()
1727 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v11_0_afmt_update_ACR()
1731 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v11_0_afmt_update_ACR()
1734 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); in dce_v11_0_afmt_update_ACR()
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| D | dce_v10_0.c | 1730 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); in dce_v10_0_afmt_update_ACR() local
1736 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); in dce_v10_0_afmt_update_ACR()
1739 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v10_0_afmt_update_ACR()
1743 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); in dce_v10_0_afmt_update_ACR()
1746 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v10_0_afmt_update_ACR()
1750 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v10_0_afmt_update_ACR()
1753 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); in dce_v10_0_afmt_update_ACR()
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| /drivers/video/fbdev/ |
| D | cg14.c | 110 u8 acr; /* Aux Control */ member
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| /drivers/atm/ |
| D | iphase.h | 255 u_short acr; member
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| D | iphase.c | 1831 vc->acr = cellrate_to_float(iadev->LineRate);
1833 vc->acr = cellrate_to_float(vcc->qos.txtp.pcr);
1835 vcc->qos.txtp.max_pcr,vc->acr);)
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