Searched refs:ccm_base (Results 1 – 4 of 4) sorted by relevance
18 #define CCM_CCR (ccm_base + 0x00)19 #define CCM_CSR (ccm_base + 0x04)20 #define CCM_CCSR (ccm_base + 0x08)21 #define CCM_CACRR (ccm_base + 0x0c)22 #define CCM_CSCMR1 (ccm_base + 0x10)23 #define CCM_CSCDR1 (ccm_base + 0x14)24 #define CCM_CSCDR2 (ccm_base + 0x18)25 #define CCM_CSCDR3 (ccm_base + 0x1c)26 #define CCM_CSCMR2 (ccm_base + 0x20)27 #define CCM_CSCDR4 (ccm_base + 0x24)[all …]
33 #define MXC_CCM_CCR (ccm_base + 0x00)34 #define MXC_CCM_CCDR (ccm_base + 0x04)35 #define MXC_CCM_CSR (ccm_base + 0x08)36 #define MXC_CCM_CCSR (ccm_base + 0x0c)37 #define MXC_CCM_CACRR (ccm_base + 0x10)38 #define MXC_CCM_CBCDR (ccm_base + 0x14)39 #define MXC_CCM_CBCMR (ccm_base + 0x18)40 #define MXC_CCM_CSCMR1 (ccm_base + 0x1c)41 #define MXC_CCM_CSCMR2 (ccm_base + 0x20)42 #define MXC_CCM_CSCDR1 (ccm_base + 0x24)[all …]
104 static void __iomem *ccm_base; variable135 if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { in imx6sl_get_arm_divider_for_wait()176 saved_arm_div = readl_relaxed(ccm_base + CACRR); in imx6sl_set_wait_clk()177 writel_relaxed(arm_div_for_wait, ccm_base + CACRR); in imx6sl_set_wait_clk()179 writel_relaxed(saved_arm_div, ccm_base + CACRR); in imx6sl_set_wait_clk()181 while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY) in imx6sl_set_wait_clk()295 ccm_base = base; in imx6sl_clocks_init()
54 #define ccm(x) (ccm_base + (x))99 static int __init __mx25_clocks_init(void __iomem *ccm_base) in __mx25_clocks_init() argument101 BUG_ON(!ccm_base); in __mx25_clocks_init()