| /drivers/edac/ |
| D | octeon_edac-lmc.c | 41 union cvmx_lmcx_mem_cfg0 cfg0; in octeon_lmc_edac_poll() local
45 cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx)); in octeon_lmc_edac_poll()
46 if (cfg0.s.sec_err || cfg0.s.ded_err) { in octeon_lmc_edac_poll()
55 if (cfg0.s.sec_err) { in octeon_lmc_edac_poll()
58 cfg0.s.sec_err = -1; /* Done, re-arm */ in octeon_lmc_edac_poll()
62 if (cfg0.s.ded_err) { in octeon_lmc_edac_poll()
65 cfg0.s.ded_err = -1; /* Done, re-arm */ in octeon_lmc_edac_poll()
69 cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx), cfg0.u64); in octeon_lmc_edac_poll()
239 union cvmx_lmcx_mem_cfg0 cfg0; in octeon_lmc_edac_probe() local
241 cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(0)); in octeon_lmc_edac_probe()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramnv10.c | 31 u32 cfg0 = nvkm_rd32(device, 0x100200); in nv10_ram_new() local
34 if (cfg0 & 0x00000001) in nv10_ram_new()
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| /drivers/clk/zte/ |
| D | clk-zx296702.c | 56 { .rate = 700000000, .cfg0 = 0x800405d1, .cfg1 = 0x04555555 },
57 { .rate = 800000000, .cfg0 = 0x80040691, .cfg1 = 0x04aaaaaa },
58 { .rate = 900000000, .cfg0 = 0x80040791, .cfg1 = 0x04000000 },
59 { .rate = 1000000000, .cfg0 = 0x80040851, .cfg1 = 0x04555555 },
60 { .rate = 1100000000, .cfg0 = 0x80040911, .cfg1 = 0x04aaaaaa },
61 { .rate = 1200000000, .cfg0 = 0x80040a11, .cfg1 = 0x04000000 },
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| D | clk.h | 37 u32 cfg0; member
54 .cfg0 = _cfg0, \
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| D | clk.c | 57 if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1) in hw_to_idx()
99 writel_relaxed(config->cfg0, zx_pll->reg_base); in zx_pll_set_rate()
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| /drivers/gpu/drm/exynos/ |
| D | exynos_drm_fimc.c | 1414 u32 cfg0, cfg1; in fimc_ippdrv_start() local
1450 cfg0 = fimc_read(ctx, EXYNOS_MSCTRL); in fimc_ippdrv_start()
1451 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK; in fimc_ippdrv_start()
1452 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY; in fimc_ippdrv_start()
1453 fimc_write(ctx, cfg0, EXYNOS_MSCTRL); in fimc_ippdrv_start()
1480 cfg0 = fimc_read(ctx, EXYNOS_CIIMGCPT); in fimc_ippdrv_start()
1481 cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC; in fimc_ippdrv_start()
1482 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC; in fimc_ippdrv_start()
1493 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN; in fimc_ippdrv_start()
1494 fimc_write(ctx, cfg0, EXYNOS_CIIMGCPT); in fimc_ippdrv_start()
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| /drivers/net/phy/ |
| D | dp83640.c | 120 int cfg0; member
541 u16 cfg0 = 0, ver; in enable_status_frames() local
544 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; in enable_status_frames()
550 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); in enable_status_frames()
623 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; in recalibrate() local
640 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); in recalibrate()
645 cfg0 = ext_read(master, PAGE5, PSF_CFG0); in recalibrate()
720 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); in recalibrate()
722 ext_write(0, master, PAGE5, PSF_CFG0, cfg0); in recalibrate()
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| /drivers/mtd/nand/ |
| D | qcom_nandc.c | 199 __le32 cfg0; member
319 u32 cfg0, cfg1; member
366 return ®s->cfg0; in offset_to_nandc_reg()
424 u32 cmd, cfg0, cfg1, ecc_bch_cfg; in update_rw_regs() local
436 cfg0 = (host->cfg0 & ~(7U << CW_PER_PAGE)) | in update_rw_regs()
442 cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) | in update_rw_regs()
450 nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0); in update_rw_regs()
1873 host->cfg0 = (cwperpage - 1) << CW_PER_PAGE in qcom_nand_host_setup()
1917 host->cfg0, host->cfg1, host->ecc_buf_cfg, host->ecc_bch_cfg, in qcom_nand_host_setup()
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| /drivers/clk/sirf/ |
| D | clk-common.c | 87 u32 cfg0 = clkc_readl(clk->regofs); in pll_clk_recalc_rate() local
88 u32 nf = (cfg0 & (BIT(13) - 1)) + 1; in pll_clk_recalc_rate()
89 u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; in pll_clk_recalc_rate()
90 u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; in pll_clk_recalc_rate()
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| /drivers/gpu/drm/i915/ |
| D | intel_dsi_panel_vbt.c | 256 u16 cfg0, cfg1; in chv_exec_gpio() local
293 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); in chv_exec_gpio()
298 vlv_iosf_sb_write(dev_priv, port, cfg0, in chv_exec_gpio()
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| /drivers/pinctrl/intel/ |
| D | pinctrl-intel.c | 247 u32 cfg0, cfg1, mode; in intel_pin_dbg_show() local
255 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); in intel_pin_dbg_show()
258 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; in intel_pin_dbg_show()
264 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); in intel_pin_dbg_show()
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| /drivers/scsi/ |
| D | dc395x.c | 196 u8 cfg0; /* Target configuration byte 0 */ member
683 eeprom->target[id].cfg0 = in eeprom_override()
1284 dcb->dev_mode = eeprom->target[dcb->target_id].cfg0; in reset_dev_param()
3750 dcb->dev_mode = eeprom->target[target].cfg0; in device_alloc()
4242 eeprom->target[0].cfg0); in print_eeprom_settings()
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