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Searched refs:cgu (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/ingenic/
Dcgu.c43 ingenic_cgu_gate_get(struct ingenic_cgu *cgu, in ingenic_cgu_gate_get() argument
46 return readl(cgu->base + info->reg) & BIT(info->bit); in ingenic_cgu_gate_get()
60 ingenic_cgu_gate_set(struct ingenic_cgu *cgu, in ingenic_cgu_gate_set() argument
63 u32 clkgr = readl(cgu->base + info->reg); in ingenic_cgu_gate_set()
70 writel(clkgr, cgu->base + info->reg); in ingenic_cgu_gate_set()
81 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_recalc_rate() local
89 clk_info = &cgu->clock_info[ingenic_clk->idx]; in ingenic_pll_recalc_rate()
93 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_recalc_rate()
94 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_recalc_rate()
95 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_recalc_rate()
[all …]
Djz4740-cgu.c54 static struct ingenic_cgu *cgu; variable
220 cgu = ingenic_cgu_new(jz4740_cgu_clocks, in jz4740_cgu_init()
222 if (!cgu) { in jz4740_cgu_init()
227 retval = ingenic_cgu_register_clocks(cgu); in jz4740_cgu_init()
235 uint32_t lcr = readl(cgu->base + CGU_REG_LCR); in jz4740_clock_set_wait_mode()
247 writel(lcr, cgu->base + CGU_REG_LCR); in jz4740_clock_set_wait_mode()
252 uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_disable_auto_suspend()
255 writel(clkgr, cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_disable_auto_suspend()
261 uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_enable_auto_suspend()
264 writel(clkgr, cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_enable_auto_suspend()
[all …]
Djz4780-cgu.c98 static struct ingenic_cgu *cgu; variable
114 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_parent()
116 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_parent()
120 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_parent()
122 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_parent()
132 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_recalc_rate()
195 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
197 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
200 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
202 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
[all …]
DMakefile1 obj-y += cgu.o
2 obj-$(CONFIG_MACH_JZ4740) += jz4740-cgu.o
3 obj-$(CONFIG_MACH_JZ4780) += jz4780-cgu.o
Dcgu.h197 struct ingenic_cgu *cgu; member
225 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu);
/drivers/clk/nxp/
DMakefile1 obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-cgu.o