| /drivers/clk/ti/ |
| D | clockdomain.c | 51 clk_hw_get_name(hw)); in omap2_clkops_enable_clkdm()
57 clk_hw_get_name(hw)); in omap2_clkops_enable_clkdm()
61 __func__, clk_hw_get_name(hw)); in omap2_clkops_enable_clkdm()
67 __func__, clk_hw_get_name(hw), clk->clkdm_name, ret); in omap2_clkops_enable_clkdm()
89 clk_hw_get_name(hw)); in omap2_clkops_disable_clkdm()
95 clk_hw_get_name(hw)); in omap2_clkops_disable_clkdm()
99 __func__, clk_hw_get_name(hw)); in omap2_clkops_disable_clkdm()
|
| D | clkt_dflt.c | 113 idlest_val, clk_hw_get_name(&clk->hw)); in _omap2_module_wait_ready()
219 __func__, clk_hw_get_name(hw), in omap2_dflt_clk_enable()
227 clk_hw_get_name(hw)); in omap2_dflt_clk_enable()
273 __func__, clk_hw_get_name(hw)); in omap2_dflt_clk_disable()
|
| D | dpll3xxx.c | 72 clk_name = clk_hw_get_name(&clk->hw); in _omap3_wait_dpll_status()
148 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
196 clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_bypass()
226 pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_stop()
455 __func__, clk_hw_get_name(hw), in omap3_noncore_dpll_enable()
592 clk_hw_get_name(hw), rate); in omap3_noncore_dpll_set_rate()
|
| D | apll.c | 53 clk_name = clk_hw_get_name(&clk->hw); in dra7_apll_enable()
288 clk_hw_get_name(&clk->hw)); in omap2_apll_enable()
|
| D | clkt_dpll.c | 308 clk_name = clk_hw_get_name(hw); in omap2_dpll_round_rate()
|
| /drivers/clk/ux500/ |
| D | clk-prcmu.c | 46 clk_hw_get_name(hw)); in clk_prcmu_unprepare()
104 (char *)clk_hw_get_name(hw), in clk_prcmu_opp_prepare()
108 __func__, clk_hw_get_name(hw)); in clk_prcmu_opp_prepare()
117 (char *)clk_hw_get_name(hw)); in clk_prcmu_opp_prepare()
132 clk_hw_get_name(hw)); in clk_prcmu_opp_unprepare()
138 (char *)clk_hw_get_name(hw)); in clk_prcmu_opp_unprepare()
154 __func__, clk_hw_get_name(hw)); in clk_prcmu_opp_volt_prepare()
177 clk_hw_get_name(hw)); in clk_prcmu_opp_volt_unprepare()
|
| D | clk-sysctrl.c | 55 __func__, clk_hw_get_name(hw)); in clk_sysctrl_unprepare()
|
| /drivers/clk/ |
| D | clk-xgene.c | 79 pr_debug("%s pll %s\n", clk_hw_get_name(hw), in xgene_clk_pll_is_enabled()
127 clk_hw_get_name(hw), fvco / nout, parent_rate, in xgene_clk_pll_recalc_rate()
471 pr_debug("%s clock enabled\n", clk_hw_get_name(hw)); in xgene_clk_enable()
479 clk_hw_get_name(hw), in xgene_clk_enable()
490 clk_hw_get_name(hw), in xgene_clk_enable()
511 pr_debug("%s clock disabled\n", clk_hw_get_name(hw)); in xgene_clk_disable()
537 pr_debug("%s clock checking\n", clk_hw_get_name(hw)); in xgene_clk_is_enabled()
540 pr_debug("%s clock is %s\n", clk_hw_get_name(hw), in xgene_clk_is_enabled()
563 clk_hw_get_name(hw), in xgene_clk_recalc_rate()
569 clk_hw_get_name(hw), parent_rate, parent_rate); in xgene_clk_recalc_rate()
[all …]
|
| D | clk-si5351.c | 442 __func__, clk_hw_get_name(hw), in si5351_pll_recalc_rate()
500 __func__, clk_hw_get_name(hw), a, b, c, in si5351_pll_round_rate()
524 __func__, clk_hw_get_name(hw), in si5351_pll_set_rate()
635 __func__, clk_hw_get_name(hw), in si5351_msynth_recalc_rate()
748 __func__, clk_hw_get_name(hw), a, b, c, divby4, in si5351_msynth_round_rate()
780 __func__, clk_hw_get_name(hw), in si5351_msynth_set_rate()
1045 __func__, clk_hw_get_name(hw), (1 << rdiv), in si5351_clkout_round_rate()
1103 __func__, clk_hw_get_name(hw), (1 << rdiv), in si5351_clkout_set_rate()
|
| /drivers/clk/sunxi-ng/ |
| D | ccu_frac.c | 70 printk("%s: Read fractional\n", clk_hw_get_name(&common->hw)); in ccu_frac_helper_read_rate()
76 clk_hw_get_name(&common->hw), cf->rates[0], cf->rates[1]); in ccu_frac_helper_read_rate()
81 clk_hw_get_name(&common->hw), reg, cf->select); in ccu_frac_helper_read_rate()
|
| D | ccu_common.c | 62 clk_hw_get_name(hw)); in sunxi_ccu_probe()
|
| /drivers/clk/st/ |
| D | clkgen-fsyn.c | 285 clk_hw_get_name(hw), __func__); in quadfs_pll_fs660c32_recalc_rate()
333 __func__, clk_hw_get_name(hw), in quadfs_pll_fs660c32_round_rate()
358 __func__, clk_hw_get_name(hw), in quadfs_pll_fs660c32_set_rate()
516 pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); in quadfs_fsynth_enable()
541 pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); in quadfs_fsynth_disable()
558 __func__, clk_hw_get_name(hw), nsb); in quadfs_fsynth_is_enabled()
752 clk_hw_get_name(hw), __func__); in quadfs_recalc_rate()
755 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); in quadfs_recalc_rate()
768 __func__, clk_hw_get_name(hw), in quadfs_round_rate()
|
| D | clk-flexgen.c | 58 pr_debug("%s: flexgen output enabled\n", clk_hw_get_name(hw)); in flexgen_enable()
72 pr_debug("%s: flexgen output disabled\n", clk_hw_get_name(hw)); in flexgen_disable()
|
| /drivers/clk/berlin/ |
| D | berlin2-pll.c | 64 pr_warn("%s has zero rfdiv\n", clk_hw_get_name(hw)); in berlin2_pll_recalc_rate()
73 clk_hw_get_name(hw), vcodivsel); in berlin2_pll_recalc_rate()
|
| D | bg2.c | 590 clk_names[SYSPLL] = clk_hw_get_name(hw); in berlin2_clock_setup()
598 clk_names[MEMPLL] = clk_hw_get_name(hw); in berlin2_clock_setup()
606 clk_names[CPUPLL] = clk_hw_get_name(hw); in berlin2_clock_setup()
|
| /drivers/clk/samsung/ |
| D | clk-pll.c | 185 drate, clk_hw_get_name(hw)); in samsung_pll35xx_set_rate()
293 drate, clk_hw_get_name(hw)); in samsung_pll36xx_set_rate()
408 drate, clk_hw_get_name(hw)); in samsung_pll45xx_set_rate()
460 __func__, clk_hw_get_name(hw)); in samsung_pll45xx_set_rate()
559 drate, clk_hw_get_name(hw)); in samsung_pll46xx_set_rate()
619 __func__, clk_hw_get_name(hw)); in samsung_pll46xx_set_rate()
777 drate, clk_hw_get_name(hw)); in samsung_s3c2410_pll_set_rate()
973 drate, clk_hw_get_name(hw)); in samsung_pll2550xx_set_rate()
1073 drate, clk_hw_get_name(hw)); in samsung_pll2650x_set_rate()
1167 drate, clk_hw_get_name(hw)); in samsung_pll2650xx_set_rate()
|
| /drivers/clk/nxp/ |
| D | clk-lpc32xx.c | 521 clk_hw_get_name(hw), in clk_pll_recalc_rate()
530 clk_hw_get_name(hw), in clk_pll_recalc_rate()
594 pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate); in clk_hclk_pll_round_rate()
623 clk_hw_get_name(hw), rate); in clk_hclk_pll_round_rate()
641 clk_hw_get_name(hw), rate, m, n, p); in clk_hclk_pll_round_rate()
644 clk_hw_get_name(hw), rate, m, n, p, o); in clk_hclk_pll_round_rate()
656 pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate); in clk_usb_pll_round_rate()
806 pr_debug("%s: 0x%x\n", clk_hw_get_name(hw), clk->enable); in clk_usb_enable()
|
| /drivers/clk/rockchip/ |
| D | clk-pll.c | 404 clk_hw_get_name(hw)); in rockchip_rk3066_pll_recalc_rate()
483 __func__, clk_hw_get_name(hw), drate, prate); in rockchip_rk3066_pll_set_rate()
489 drate, clk_hw_get_name(hw)); in rockchip_rk3066_pll_set_rate()
543 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, in rockchip_rk3066_pll_init()
548 __func__, clk_hw_get_name(hw)); in rockchip_rk3066_pll_init()
|
| D | clk-inverter.c | 53 __func__, degrees, clk_hw_get_name(hw)); in rockchip_inv_set_phase()
|
| D | clk-mmc-phase.c | 128 clk_hw_get_name(hw), degrees, delay_num, in rockchip_mmc_set_phase()
|
| /drivers/clk/microchip/ |
| D | clk-core.c | 428 __func__, clk_hw_get_name(hw), req->rate); in roclk_determine_rate()
433 clk_hw_get_name(hw), req->rate, in roclk_determine_rate()
434 clk_hw_get_name(best_parent_clk), best_parent_rate, in roclk_determine_rate()
460 pr_err("%s: poll failed, clk active\n", clk_hw_get_name(hw)); in roclk_set_parent()
883 clk_hw_get_name(hw), nosc, cosc); in sclk_set_parent()
|
| /drivers/clk/qcom/ |
| D | clk-branch.c | 78 const char *name = clk_hw_get_name(&br->clkr.hw); in clk_branch_wait()
|
| D | clk-rcg2.c | 83 __func__, clk_hw_get_name(hw)); in clk_rcg2_get_parent()
92 const char *name = clk_hw_get_name(hw); in update_config()
306 const char *name = clk_hw_get_name(hw); in clk_rcg2_shared_force_enable()
|
| /drivers/clk/pistachio/ |
| D | clk-pll.c | 203 const char *name = clk_hw_get_name(hw); in pll_gf40lp_frac_set_rate()
360 const char *name = clk_hw_get_name(hw); in pll_gf40lp_laint_set_rate()
|
| /drivers/clk/renesas/ |
| D | clk-div6.c | 143 __func__, clk_hw_get_name(hw), hw_index); in cpg_div6_clock_get_parent()
|