Home
last modified time | relevance | path

Searched refs:clk_regs (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/radeon/
Drv740_dpm.c126 u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; in rv740_populate_sclk_value()
127 u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2; in rv740_populate_sclk_value()
128 u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3; in rv740_populate_sclk_value()
129 u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum; in rv740_populate_sclk_value()
130 u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2; in rv740_populate_sclk_value()
192 u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl; in rv740_populate_mclk_value()
193 u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2; in rv740_populate_mclk_value()
194 u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl; in rv740_populate_mclk_value()
195 u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2; in rv740_populate_mclk_value()
196 u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl; in rv740_populate_mclk_value()
[all …]
Drv730_dpm.c46 u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl; in rv730_populate_sclk_value()
47 u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2; in rv730_populate_sclk_value()
48 u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3; in rv730_populate_sclk_value()
49 u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum; in rv730_populate_sclk_value()
50 u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2; in rv730_populate_sclk_value()
124 u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl; in rv730_populate_mclk_value()
125 u32 dll_cntl = pi->clk_regs.rv730.dll_cntl; in rv730_populate_mclk_value()
126 u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl; in rv730_populate_mclk_value()
127 u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2; in rv730_populate_mclk_value()
128 u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3; in rv730_populate_mclk_value()
[all …]
Drv770_dpm.c393 pi->clk_regs.rv770.mpll_ad_func_cntl; in rv770_populate_mclk_value()
395 pi->clk_regs.rv770.mpll_ad_func_cntl_2; in rv770_populate_mclk_value()
397 pi->clk_regs.rv770.mpll_dq_func_cntl; in rv770_populate_mclk_value()
399 pi->clk_regs.rv770.mpll_dq_func_cntl_2; in rv770_populate_mclk_value()
401 pi->clk_regs.rv770.mclk_pwrmgt_cntl; in rv770_populate_mclk_value()
402 u32 dll_cntl = pi->clk_regs.rv770.dll_cntl; in rv770_populate_mclk_value()
491 pi->clk_regs.rv770.cg_spll_func_cntl; in rv770_populate_sclk_value()
493 pi->clk_regs.rv770.cg_spll_func_cntl_2; in rv770_populate_sclk_value()
495 pi->clk_regs.rv770.cg_spll_func_cntl_3; in rv770_populate_sclk_value()
497 pi->clk_regs.rv770.cg_spll_spread_spectrum; in rv770_populate_sclk_value()
[all …]
Dcypress_dpm.c481 pi->clk_regs.rv770.mpll_ad_func_cntl; in cypress_populate_mclk_value()
483 pi->clk_regs.rv770.mpll_ad_func_cntl_2; in cypress_populate_mclk_value()
485 pi->clk_regs.rv770.mpll_dq_func_cntl; in cypress_populate_mclk_value()
487 pi->clk_regs.rv770.mpll_dq_func_cntl_2; in cypress_populate_mclk_value()
489 pi->clk_regs.rv770.mclk_pwrmgt_cntl; in cypress_populate_mclk_value()
491 pi->clk_regs.rv770.dll_cntl; in cypress_populate_mclk_value()
492 u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1; in cypress_populate_mclk_value()
493 u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2; in cypress_populate_mclk_value()
1244 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl); in cypress_populate_smc_initial_state()
1246 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2); in cypress_populate_smc_initial_state()
[all …]
Drv770_dpm.h95 union r7xx_clock_registers clk_regs; member
/drivers/clk/tegra/
Dclk-emc.c80 void __iomem *clk_regs; member
108 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
165 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_get_parent()
246 car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_set_timing()
254 writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC); in emc_set_timing()
488 tegra->clk_regs = base; in tegra_clk_register_emc()
/drivers/clk/samsung/
Dclk-exynos7.c202 .clk_regs = topc_clk_regs,
394 .clk_regs = top0_clk_regs,
571 .clk_regs = top1_clk_regs,
616 .clk_regs = ccore_clk_regs,
683 .clk_regs = peric0_clk_regs,
807 .clk_regs = peric1_clk_regs,
862 .clk_regs = peris_clk_regs,
972 .clk_regs = fsys0_clk_regs,
1103 .clk_regs = fsys1_clk_regs,
1216 .clk_regs = mscl_clk_regs,
[all …]
Dclk-exynos5260.c142 .clk_regs = aud_clk_regs,
332 .clk_regs = disp_clk_regs,
396 .clk_regs = egl_clk_regs,
496 .clk_regs = fsys_clk_regs,
587 .clk_regs = g2d_clk_regs,
650 .clk_regs = g3d_clk_regs,
783 .clk_regs = gscl_clk_regs,
902 .clk_regs = isp_clk_regs,
966 .clk_regs = kfc_clk_regs,
1022 .clk_regs = mfc_clk_regs,
[all …]
Dclk-exynos5433.c786 .clk_regs = top_clk_regs,
856 .clk_regs = cpif_clk_regs,
1508 .clk_regs = mif_clk_regs,
1699 .clk_regs = peric_clk_regs,
1891 .clk_regs = peris_clk_regs,
2295 .clk_regs = fsys_clk_regs,
2419 .clk_regs = g2d_clk_regs,
2840 .clk_regs = disp_clk_regs,
3010 .clk_regs = aud_clk_regs,
3150 .clk_regs = bus01_clk_regs,
[all …]
Dclk.c418 if (cmu->clk_regs) in samsung_cmu_register_one()
419 samsung_clk_sleep_init(reg_base, cmu->clk_regs, in samsung_cmu_register_one()
Dclk-exynos4415.c939 .clk_regs = exynos4415_cmu_clk_regs,
1013 .clk_regs = exynos4415_cmu_dmc_clk_regs,
Dclk-exynos3250.c787 .clk_regs = exynos3250_cmu_clk_regs,
928 .clk_regs = exynos3250_cmu_dmc_clk_regs,
Dclk.h354 const unsigned long *clk_regs; member
/drivers/thermal/tegra/
Dsoctherm.c231 void __iomem *clk_regs; member
253 writel(value, (ts->clk_regs + reg)); in clk_writel()
265 return readl(ts->clk_regs + reg); in clk_readl()
1322 tegra->clk_regs = devm_ioremap_resource(&pdev->dev, res); in tegra_soctherm_probe()
1323 if (IS_ERR(tegra->clk_regs)) { in tegra_soctherm_probe()
1325 return PTR_ERR(tegra->clk_regs); in tegra_soctherm_probe()
/drivers/gpu/drm/amd/amdgpu/
Dsi_dpm.h552 union r7xx_clock_registers clk_regs; member