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Searched refs:clk_s (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/radeon/
Drv740_dpm.c165 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv740_populate_sclk_value() local
166 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); in rv740_populate_sclk_value()
169 cg_spll_spread_spectrum |= CLK_S(clk_s); in rv740_populate_sclk_value()
254 u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); in rv740_populate_mclk_value() local
256 (dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000); in rv740_populate_mclk_value()
262 mpll_ss2 |= CLKS(clk_s); in rv740_populate_mclk_value()
Drv730_dpm.c97 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv730_populate_sclk_value() local
98 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000); in rv730_populate_sclk_value()
101 cg_spll_spread_spectrum |= CLK_S(clk_s); in rv730_populate_sclk_value()
173 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv730_populate_mclk_value() local
174 u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000); in rv730_populate_mclk_value()
177 mpll_ss |= CLK_S(clk_s); in rv730_populate_mclk_value()
Drv6xx_dpm.c316 u32 index, u32 clk_s) in rv6xx_set_engine_spread_spectrum_clk_s() argument
319 CLKS(clk_s), ~CLKS_MASK); in rv6xx_set_engine_spread_spectrum_clk_s()
341 u32 clk_s) in rv6xx_set_memory_spread_spectrum_clk_s() argument
343 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK); in rv6xx_set_memory_spread_spectrum_clk_s()
556 u32 vco_freq, clk_v, clk_s; in rv6xx_program_engine_spread_spectrum() local
573 clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate, in rv6xx_program_engine_spread_spectrum()
577 rv6xx_set_engine_spread_spectrum_clk_s(rdev, level, clk_s); in rv6xx_program_engine_spread_spectrum()
659 u32 vco_freq = 0, clk_v, clk_s; in rv6xx_program_mclk_spread_spectrum_parameters() local
691 clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate, in rv6xx_program_mclk_spread_spectrum_parameters()
695 rv6xx_set_memory_spread_spectrum_clk_s(rdev, clk_s); in rv6xx_program_mclk_spread_spectrum_parameters()
Dni_dpm.c2044 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ni_calculate_sclk_params() local
2045 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); in ni_calculate_sclk_params()
2048 cg_spll_spread_spectrum |= CLK_S(clk_s); in ni_calculate_sclk_params()
2096 u32 clk_s; in ni_init_smc_spll_table() local
2116 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; in ni_init_smc_spll_table()
2126 if (clk_s & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) in ni_init_smc_spll_table()
2129 if (clk_s & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) in ni_init_smc_spll_table()
2143 ((clk_s << SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK); in ni_init_smc_spll_table()
2242 u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); in ni_populate_mclk_value() local
2244 (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625); in ni_populate_mclk_value()
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Dcypress_dpm.c561 u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); in cypress_populate_mclk_value() local
563 (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625); in cypress_populate_mclk_value()
569 mpll_ss2 |= CLKS(clk_s); in cypress_populate_mclk_value()
Drv770_dpm.c544 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv770_populate_sclk_value() local
545 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000); in rv770_populate_sclk_value()
548 cg_spll_spread_spectrum |= CLKS(clk_s); in rv770_populate_sclk_value()
Dsi_dpm.c2851 u32 clk_s, clk_v; in si_init_smc_spll_table() local
2871 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; in si_init_smc_spll_table()
2882 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) in si_init_smc_spll_table()
2895 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); in si_init_smc_spll_table()
4883 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in si_calculate_sclk_params() local
4884 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); in si_calculate_sclk_params()
4887 cg_spll_spread_spectrum |= CLK_S(clk_s); in si_calculate_sclk_params()
Dci_dpm.c3175 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ci_calculate_sclk_params() local
3176 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); in ci_calculate_sclk_params()
3179 cg_spll_spread_spectrum |= CLK_S(clk_s); in ci_calculate_sclk_params()
/drivers/gpu/drm/amd/powerplay/smumgr/
Dfiji_smc.c677 uint32_t clk_s = ref_clock * 5 / in fiji_calculate_sclk_params() local
681 fbdiv / (clk_s * 10000); in fiji_calculate_sclk_params()
684 CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s); in fiji_calculate_sclk_params()
/drivers/gpu/drm/amd/amdgpu/
Dsi_dpm.c2948 u32 clk_s, clk_v; in si_init_smc_spll_table() local
2967 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; in si_init_smc_spll_table()
2978 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) in si_init_smc_spll_table()
2991 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); in si_init_smc_spll_table()
5363 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in si_calculate_sclk_params() local
5364 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); in si_calculate_sclk_params()
5367 cg_spll_spread_spectrum |= CLK_S(clk_s); in si_calculate_sclk_params()
Dci_dpm.c3309 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ci_calculate_sclk_params() local
3310 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); in ci_calculate_sclk_params()
3313 cg_spll_spread_spectrum |= (clk_s << CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT); in ci_calculate_sclk_params()