| /drivers/cpufreq/ |
| D | tegra20-cpufreq.c | 103 clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */ in tegra_target()
105 clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */ in tegra_target()
107 clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */ in tegra_target()
116 ret = clk_set_rate(pll_x_clk, rate * 1000); in tegra_target()
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| D | davinci-cpufreq.c | 58 ret = clk_set_rate(armclk, idx); in davinci_target()
63 ret = clk_set_rate(cpufreq.asyncclk, cpufreq.asyncrate); in davinci_target()
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| D | loongson2_cpufreq.c | 68 clk_set_rate(policy->clk, freq * 1000); in loongson2_cpufreq_target()
98 ret = clk_set_rate(cpuclk, rate * 1000); in loongson2_cpufreq_cpu_init()
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| D | s3c64xx-cpufreq.c | 80 ret = clk_set_rate(policy->clk, new_freq * 1000); in s3c64xx_cpufreq_set_target()
95 if (clk_set_rate(policy->clk, old_freq * 1000) < 0) in s3c64xx_cpufreq_set_target()
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| D | omap-cpufreq.c | 94 ret = clk_set_rate(policy->clk, new_freq * 1000); in omap_target()
102 clk_set_rate(policy->clk, old_freq * 1000); in omap_target()
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| D | spear-cpufreq.c | 88 ret = clk_set_rate(sys_pclk, newfreq); in spear1340_set_cpu_rate()
145 ret = clk_set_rate(spear_cpufreq.clk, newfreq); in spear_cpufreq_target()
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| D | imx6q-cpufreq.c | 113 clk_set_rate(arm_clk, (old_freq >> 1) * 1000); in imx6q_set_target()
125 clk_set_rate(pll1_sys_clk, new_freq * 1000); in imx6q_set_target()
131 ret = clk_set_rate(arm_clk, new_freq * 1000); in imx6q_set_target()
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| D | dbx500-cpufreq.c | 26 return clk_set_rate(armss_clk, freq_table[index].frequency * 1000); in dbx500_cpufreq_target()
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| D | unicore2-cpufreq.c | 48 ret = clk_set_rate(policy->clk, target_freq * 1000); in ucv2_target()
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| /drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-sunxi.c | 57 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); in sun7i_gmac_init()
61 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE); in sun7i_gmac_init()
97 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); in sun7i_fix_speed()
101 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE); in sun7i_fix_speed()
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| /drivers/clk/imx/ |
| D | clk-imx6sx.c | 516 clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000); in imx6sx_clocks_init()
534 clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000); in imx6sx_clocks_init()
535 clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000); in imx6sx_clocks_init()
536 clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000); in imx6sx_clocks_init()
539 clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000); in imx6sx_clocks_init()
542 clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000); in imx6sx_clocks_init()
545 clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000); in imx6sx_clocks_init()
550 clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000); in imx6sx_clocks_init()
551 clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000); in imx6sx_clocks_init()
552 clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000); in imx6sx_clocks_init()
[all …]
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| D | clk-cpu.c | 58 ret = clk_set_rate(cpu->pll, rate); in clk_cpu_set_rate()
67 clk_set_rate(cpu->div, rate); in clk_cpu_set_rate()
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| D | clk-imx51-imx53.c | 382 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); in mx50_clocks_init()
383 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); in mx50_clocks_init()
390 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); in mx50_clocks_init()
459 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); in mx51_clocks_init()
460 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); in mx51_clocks_init()
590 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); in mx53_clocks_init()
591 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); in mx53_clocks_init()
604 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); in mx53_clocks_init()
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| D | clk-vf610.c | 449 clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); in vf610_clocks_init()
450 clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); in vf610_clocks_init()
451 clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2); in vf610_clocks_init()
454 clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2); in vf610_clocks_init()
455 clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2); in vf610_clocks_init()
456 clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2); in vf610_clocks_init()
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| D | clk-imx6ul.c | 416 clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000); in imx6ul_clocks_init()
425 clk_set_rate(clks[IMX6UL_CLK_AHB], 132000000); in imx6ul_clocks_init()
430 clk_set_rate(clks[IMX6UL_CLK_ENET_REF], 50000000); in imx6ul_clocks_init()
431 clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000); in imx6ul_clocks_init()
432 clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000); in imx6ul_clocks_init()
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| /drivers/clk/ti/ |
| D | clk-54xx.c | 242 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); in omap5xxx_dt_clk_init()
248 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2); in omap5xxx_dt_clk_init()
253 rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); in omap5xxx_dt_clk_init()
258 rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2); in omap5xxx_dt_clk_init()
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| D | clk-7xx.c | 322 rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); in dra7xx_dt_clk_init()
327 rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ); in dra7xx_dt_clk_init()
332 rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2); in dra7xx_dt_clk_init()
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| D | clk-44xx.c | 286 rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ); in omap4xxx_dt_clk_init()
301 rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ); in omap4xxx_dt_clk_init()
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| /drivers/gpu/drm/arm/ |
| D | malidp_crtc.c | 67 clk_set_rate(hwdev->mclk, crtc->state->adjusted_mode.crtc_clock * 1000); in malidp_crtc_enable()
68 clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000); in malidp_crtc_enable()
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| /drivers/mmc/host/ |
| D | dw_mmc-k3.c | 45 ret = clk_set_rate(host->ciu_clk, ios->clock); in dw_mci_k3_set_ios()
127 ret = clk_set_rate(host->biu_clk, clock); in dw_mci_hi6220_set_ios()
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| D | sdhci-st.c | 173 clk_set_rate(pltfm_host->clk, mhost->f_max); in st_mmcss_cconfig()
177 clk_set_rate(pltfm_host->clk, mhost->f_max); in st_mmcss_cconfig()
181 clk_set_rate(pltfm_host->clk, 50000000); in st_mmcss_cconfig()
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| /drivers/net/ethernet/arc/ |
| D | emac_rockchip.c | 203 err = clk_set_rate(priv->refclk, 50000000); in emac_rockchip_probe()
224 err = clk_set_rate(priv->macclk, 25000000); in emac_rockchip_probe()
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| /drivers/net/ethernet/qualcomm/emac/ |
| D | emac.c | 482 ret = clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 19200000); in emac_clks_phase1_init()
495 ret = clk_set_rate(adpt->clk[EMAC_CLK_TX], 125000000); in emac_clks_phase2_init()
503 ret = clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 125000000); in emac_clks_phase2_init()
507 ret = clk_set_rate(adpt->clk[EMAC_CLK_MDIO], 25000000); in emac_clks_phase2_init()
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| /drivers/devfreq/ |
| D | exynos-bus.c | 135 ret = clk_set_rate(bus->clk, new_freq); in exynos_bus_target()
138 clk_set_rate(bus->clk, old_freq); in exynos_bus_target()
238 ret = clk_set_rate(bus->clk, new_freq); in exynos_bus_passive_target()
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| /drivers/gpu/drm/armada/ |
| D | armada_510.c | 72 clk_set_rate(clk, ref); in armada510_crtc_compute_clock()
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