| /drivers/clk/imx/ |
| D | clk-imx7d.c | 45 static struct clk *clks[IMX7D_CLK_END]; variable
395 &clks[IMX7D_UART1_ROOT_CLK],
396 &clks[IMX7D_UART2_ROOT_CLK],
397 &clks[IMX7D_UART3_ROOT_CLK],
398 &clks[IMX7D_UART4_ROOT_CLK],
399 &clks[IMX7D_UART5_ROOT_CLK],
400 &clks[IMX7D_UART6_ROOT_CLK],
401 &clks[IMX7D_UART7_ROOT_CLK],
411 clks[IMX7D_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx7d_clocks_init()
412 clks[IMX7D_OSC_24M_CLK] = of_clk_get_by_name(ccm_node, "osc"); in imx7d_clocks_init()
[all …]
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| D | clk-imx6sx.c | 92 static struct clk *clks[IMX6SX_CLK_CLK_END]; variable
141 &clks[IMX6SX_CLK_UART_IPG],
142 &clks[IMX6SX_CLK_UART_SERIAL],
152 clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx6sx_clocks_init()
154 clks[IMX6SX_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); in imx6sx_clocks_init()
155 clks[IMX6SX_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); in imx6sx_clocks_init()
158 clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); in imx6sx_clocks_init()
159 clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); in imx6sx_clocks_init()
162 clks[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); in imx6sx_clocks_init()
168 …clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
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| D | clk-imx6ul.c | 68 static struct clk *clks[IMX6UL_CLK_END]; variable
112 clks[IMX6UL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx6ul_clocks_init()
114 clks[IMX6UL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); in imx6ul_clocks_init()
115 clks[IMX6UL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); in imx6ul_clocks_init()
118 clks[IMX6UL_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); in imx6ul_clocks_init()
119 clks[IMX6UL_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); in imx6ul_clocks_init()
125 …clks[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
126 …clks[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
127 …clks[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
128 …clks[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_s… in imx6ul_clocks_init()
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| D | clk-imx6sl.c | 102 static struct clk *clks[IMX6SL_CLK_END]; variable
189 &clks[IMX6SL_CLK_UART],
190 &clks[IMX6SL_CLK_UART_SERIAL],
201 clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx6sl_clocks_init()
202 clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); in imx6sl_clocks_init()
203 clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); in imx6sl_clocks_init()
205 clks[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); in imx6sl_clocks_init()
212 …clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
213 …clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
214 …clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
[all …]
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| /drivers/clk/hisilicon/ |
| D | clk.c | 62 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
94 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
105 int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, in hisi_clk_register_fixed_rate() argument
112 clk = clk_register_fixed_rate(NULL, clks[i].name, in hisi_clk_register_fixed_rate()
113 clks[i].parent_name, in hisi_clk_register_fixed_rate()
114 clks[i].flags, in hisi_clk_register_fixed_rate()
115 clks[i].fixed_rate); in hisi_clk_register_fixed_rate()
118 __func__, clks[i].name); in hisi_clk_register_fixed_rate()
121 data->clk_data.clks[clks[i].id] = clk; in hisi_clk_register_fixed_rate()
128 clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]); in hisi_clk_register_fixed_rate()
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| D | clk-hix5hd2.c | 256 hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums, in hix5hd2_clk_register_complex() argument
271 init.name = clks[i].name; in hix5hd2_clk_register_complex()
272 if (clks[i].type == TYPE_ETHER) in hix5hd2_clk_register_complex()
279 (clks[i].parent_name ? &clks[i].parent_name : NULL); in hix5hd2_clk_register_complex()
280 init.num_parents = (clks[i].parent_name ? 1 : 0); in hix5hd2_clk_register_complex()
282 p_clk->ctrl_reg = base + clks[i].ctrl_reg; in hix5hd2_clk_register_complex()
283 p_clk->ctrl_clk_mask = clks[i].ctrl_clk_mask; in hix5hd2_clk_register_complex()
284 p_clk->ctrl_rst_mask = clks[i].ctrl_rst_mask; in hix5hd2_clk_register_complex()
285 p_clk->phy_reg = base + clks[i].phy_reg; in hix5hd2_clk_register_complex()
286 p_clk->phy_clk_mask = clks[i].phy_clk_mask; in hix5hd2_clk_register_complex()
[all …]
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| /drivers/clk/mmp/ |
| D | clk.c | 20 unit->clk_data.clks = clk_table; in mmp_clk_init()
26 struct mmp_param_fixed_rate_clk *clks, in mmp_register_fixed_rate_clks() argument
33 clk = clk_register_fixed_rate(NULL, clks[i].name, in mmp_register_fixed_rate_clks()
34 clks[i].parent_name, in mmp_register_fixed_rate_clks()
35 clks[i].flags, in mmp_register_fixed_rate_clks()
36 clks[i].fixed_rate); in mmp_register_fixed_rate_clks()
39 __func__, clks[i].name); in mmp_register_fixed_rate_clks()
42 if (clks[i].id) in mmp_register_fixed_rate_clks()
43 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
48 struct mmp_param_fixed_factor_clk *clks, in mmp_register_fixed_factor_clks() argument
[all …]
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| /drivers/clk/mxs/ |
| D | clk-imx28.c | 151 static struct clk *clks[clk_max]; variable
173 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx28_clocks_init()
174 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
175 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
176 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
177 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
178 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
179 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
180 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
181 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); in mx28_clocks_init()
[all …]
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| D | clk-imx23.c | 96 static struct clk *clks[clk_max]; variable
118 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx23_clocks_init()
119 clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); in mx23_clocks_init()
120 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); in mx23_clocks_init()
121 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); in mx23_clocks_init()
122 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); in mx23_clocks_init()
123 clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); in mx23_clocks_init()
124 clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll)); in mx23_clocks_init()
125 clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix)); in mx23_clocks_init()
126 clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io)); in mx23_clocks_init()
[all …]
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| /drivers/clk/axis/ |
| D | clk-artpec6.c | 46 struct clk **clks; in of_artpec6_clkctrl_setup() local
59 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
62 clks[i] = ERR_PTR(-EPROBE_DEFER); in of_artpec6_clkctrl_setup()
88 clks[ARTPEC6_CLK_CPU] = in of_artpec6_clkctrl_setup()
91 clks[ARTPEC6_CLK_CPU_PERIPH] = in of_artpec6_clkctrl_setup()
95 clks[ARTPEC6_CLK_UART_PCLK] = in of_artpec6_clkctrl_setup()
97 clks[ARTPEC6_CLK_UART_REFCLK] = in of_artpec6_clkctrl_setup()
101 clks[ARTPEC6_CLK_SPI_PCLK] = in of_artpec6_clkctrl_setup()
103 clks[ARTPEC6_CLK_SPI_SSPCLK] = in of_artpec6_clkctrl_setup()
107 clks[ARTPEC6_CLK_DBG_PCLK] = in of_artpec6_clkctrl_setup()
[all …]
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| /drivers/clk/zynq/ |
| D | clkc.c | 72 static struct clk *clks[clk_max]; variable
158 clks[fclk] = clk_register_gate(NULL, clk_name, in zynq_clk_register_fclk()
163 if (clk_prepare_enable(clks[fclk])) in zynq_clk_register_fclk()
182 clks[fclk] = ERR_PTR(-ENOMEM); in zynq_clk_register_fclk()
209 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, in zynq_clk_register_periph_clk()
212 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, in zynq_clk_register_periph_clk()
221 clks[clk0] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
223 clks[clk1] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
273 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], in zynq_clk_setup()
279 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], in zynq_clk_setup()
[all …]
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| /drivers/clk/versatile/ |
| D | clk-impd1.c | 35 struct clk_lookup *clks[15]; member
108 imc->clks[0] = clkdev_alloc(pclk, "apb_pclk", "lm%x:01000", id); in integrator_impd1_clk_init()
109 imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:01000", id); in integrator_impd1_clk_init()
118 imc->clks[2] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00700", id); in integrator_impd1_clk_init()
119 imc->clks[3] = clkdev_alloc(clk, NULL, "lm%x:00700", id); in integrator_impd1_clk_init()
126 imc->clks[4] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00100", id); in integrator_impd1_clk_init()
127 imc->clks[5] = clkdev_alloc(clk, NULL, "lm%x:00100", id); in integrator_impd1_clk_init()
128 imc->clks[6] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00200", id); in integrator_impd1_clk_init()
129 imc->clks[7] = clkdev_alloc(clk, NULL, "lm%x:00200", id); in integrator_impd1_clk_init()
135 imc->clks[8] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00300", id); in integrator_impd1_clk_init()
[all …]
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| /drivers/clk/microchip/ |
| D | clk-pic32mzda.c | 135 struct clk *clks[MAXCLKS]; member
164 struct clk **clks; in pic32mzda_clk_probe() local
180 clks = &cd->clks[0]; in pic32mzda_clk_probe()
183 clks[POSCCLK] = clk_register_fixed_rate(&pdev->dev, "posc_clk", NULL, in pic32mzda_clk_probe()
185 clks[FRCCLK] = clk_register_fixed_rate(&pdev->dev, "frc_clk", NULL, in pic32mzda_clk_probe()
187 clks[BFRCCLK] = clk_register_fixed_rate(&pdev->dev, "bfrc_clk", NULL, in pic32mzda_clk_probe()
189 clks[LPRCCLK] = clk_register_fixed_rate(&pdev->dev, "lprc_clk", NULL, in pic32mzda_clk_probe()
191 clks[UPLLCLK] = clk_register_fixed_rate(&pdev->dev, "usbphy_clk", NULL, in pic32mzda_clk_probe()
196 clks[SOSCCLK] = pic32_sosc_clk_register(&sosc_clk, core); in pic32mzda_clk_probe()
199 clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk", in pic32mzda_clk_probe()
[all …]
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| /drivers/usb/dwc3/ |
| D | dwc3-of-simple.c | 35 struct clk **clks; member
50 simple->clks = devm_kcalloc(dev, simple->num_clocks, in dwc3_of_simple_clk_init()
52 if (!simple->clks) in dwc3_of_simple_clk_init()
62 clk_disable_unprepare(simple->clks[i]); in dwc3_of_simple_clk_init()
63 clk_put(simple->clks[i]); in dwc3_of_simple_clk_init()
71 clk_disable_unprepare(simple->clks[i]); in dwc3_of_simple_clk_init()
72 clk_put(simple->clks[i]); in dwc3_of_simple_clk_init()
79 simple->clks[i] = clk; in dwc3_of_simple_clk_init()
108 clk_disable_unprepare(simple->clks[i]); in dwc3_of_simple_probe()
109 clk_put(simple->clks[i]); in dwc3_of_simple_probe()
[all …]
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| /drivers/clk/tegra/ |
| D | clk.c | 78 static struct clk **clks; variable
211 clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL); in tegra_clk_init()
212 if (!clks) in tegra_clk_init()
217 return clks; in tegra_clk_init()
221 struct clk *clks[], int clk_max) in tegra_init_dup_clks() argument
226 clk = clks[dup_list->clk_id]; in tegra_init_dup_clks()
233 struct clk *clks[], int clk_max) in tegra_init_from_table() argument
238 clk = clks[tbl->clk_id]; in tegra_init_from_table()
248 struct clk *parent = clks[tbl->parent_id]; in tegra_init_from_table()
290 if (IS_ERR(clks[i])) { in tegra_add_of_provider()
[all …]
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| D | clk-tegra20.c | 166 static struct clk **clks; variable
639 clks[TEGRA20_CLK_PLL_C] = clk; in tegra20_pll_init()
648 clks[TEGRA20_CLK_PLL_C_OUT1] = clk; in tegra20_pll_init()
654 clks[TEGRA20_CLK_PLL_M] = clk; in tegra20_pll_init()
663 clks[TEGRA20_CLK_PLL_M_OUT1] = clk; in tegra20_pll_init()
668 clks[TEGRA20_CLK_PLL_X] = clk; in tegra20_pll_init()
673 clks[TEGRA20_CLK_PLL_U] = clk; in tegra20_pll_init()
678 clks[TEGRA20_CLK_PLL_D] = clk; in tegra20_pll_init()
683 clks[TEGRA20_CLK_PLL_D_OUT0] = clk; in tegra20_pll_init()
688 clks[TEGRA20_CLK_PLL_A] = clk; in tegra20_pll_init()
[all …]
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| /drivers/clk/pxa/ |
| D | clk-pxa.c | 25 .clks = pxa_clocks,
80 int __init clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks) in clk_pxa_cken_init() argument
88 pxa_clk->is_in_low_power = clks[i].is_in_low_power; in clk_pxa_cken_init()
89 pxa_clk->lp = clks[i].lp; in clk_pxa_cken_init()
90 pxa_clk->hp = clks[i].hp; in clk_pxa_cken_init()
91 pxa_clk->gate = clks[i].gate; in clk_pxa_cken_init()
93 clk = clk_register_composite(NULL, clks[i].name, in clk_pxa_cken_init()
94 clks[i].parent_names, 2, in clk_pxa_cken_init()
98 clks[i].flags); in clk_pxa_cken_init()
99 clkdev_pxa_register(clks[i].ckid, clks[i].con_id, in clk_pxa_cken_init()
[all …]
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| /drivers/clk/sunxi/ |
| D | clk-a10-pll2.c | 50 struct clk **clks, *base_clk, *prediv_clk; in sun4i_pll2_setup() local
65 clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL); in sun4i_pll2_setup()
66 if (!clks) in sun4i_pll2_setup()
130 clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
135 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X])); in sun4i_pll2_setup()
145 clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
149 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X])); in sun4i_pll2_setup()
154 clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
158 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X])); in sun4i_pll2_setup()
163 clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
[all …]
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| /drivers/clk/mediatek/ |
| D | clk-mtk.c | 36 clk_data->clks = kcalloc(clk_num, sizeof(*clk_data->clks), GFP_KERNEL); in mtk_alloc_clk_data()
37 if (!clk_data->clks) in mtk_alloc_clk_data()
43 clk_data->clks[i] = ERR_PTR(-ENOENT); in mtk_alloc_clk_data()
52 void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, in mtk_clk_register_fixed_clks() argument
59 const struct mtk_fixed_clk *rc = &clks[i]; in mtk_clk_register_fixed_clks()
71 clk_data->clks[rc->id] = clk; in mtk_clk_register_fixed_clks()
75 void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, in mtk_clk_register_factors() argument
82 const struct mtk_fixed_factor *ff = &clks[i]; in mtk_clk_register_factors()
94 clk_data->clks[ff->id] = clk; in mtk_clk_register_factors()
99 const struct mtk_gate *clks, in mtk_clk_register_gates() argument
[all …]
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| /drivers/sh/clk/ |
| D | cpg.c | 94 int __init sh_clk_mstp_register(struct clk *clks, int nr) in sh_clk_mstp_register() argument
101 clkp = clks + k; in sh_clk_mstp_register()
241 static int __init sh_clk_div_register_ops(struct clk *clks, int nr, in sh_clk_div_register_ops() argument
259 clkp = clks + k; in sh_clk_div_register_ops()
336 int __init sh_clk_div6_register(struct clk *clks, int nr) in sh_clk_div6_register() argument
338 return sh_clk_div_register_ops(clks, nr, &sh_clk_div6_table, in sh_clk_div6_register()
342 int __init sh_clk_div6_reparent_register(struct clk *clks, int nr) in sh_clk_div6_reparent_register() argument
344 return sh_clk_div_register_ops(clks, nr, &sh_clk_div6_table, in sh_clk_div6_reparent_register()
389 int __init sh_clk_div4_register(struct clk *clks, int nr, in sh_clk_div4_register() argument
392 return sh_clk_div_register_ops(clks, nr, table, &sh_clk_div_clk_ops); in sh_clk_div4_register()
[all …]
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| /drivers/clk/pistachio/ |
| D | clk.c | 27 p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL); in pistachio_clk_alloc_provider()
28 if (!p->clk_data.clks) in pistachio_clk_alloc_provider()
41 kfree(p->clk_data.clks); in pistachio_clk_alloc_provider()
52 if (IS_ERR(p->clk_data.clks[i])) in pistachio_clk_register_provider()
54 PTR_ERR(p->clk_data.clks[i])); in pistachio_clk_register_provider()
72 p->clk_data.clks[gate[i].id] = clk; in pistachio_clk_register_gate()
90 p->clk_data.clks[mux[i].id] = clk; in pistachio_clk_register_mux()
106 p->clk_data.clks[div[i].id] = clk; in pistachio_clk_register_div()
120 p->clk_data.clks[ff[i].id] = clk; in pistachio_clk_register_fixed_factor()
131 struct clk *clk = p->clk_data.clks[clk_ids[i]]; in pistachio_clk_force_enable()
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| /drivers/clk/renesas/ |
| D | clk-mstp.c | 180 struct clk **clks; in cpg_mstp_clocks_init() local
184 clks = kmalloc_array(MSTP_MAX_CLOCKS, sizeof(*clks), GFP_KERNEL); in cpg_mstp_clocks_init()
185 if (group == NULL || clks == NULL) { in cpg_mstp_clocks_init()
187 kfree(clks); in cpg_mstp_clocks_init()
193 group->data.clks = clks; in cpg_mstp_clocks_init()
201 kfree(clks); in cpg_mstp_clocks_init()
209 clks[i] = ERR_PTR(-ENOENT); in cpg_mstp_clocks_init()
239 clks[clkidx] = cpg_mstp_clock_register(name, parent_name, in cpg_mstp_clocks_init()
241 if (!IS_ERR(clks[clkidx])) { in cpg_mstp_clocks_init()
252 clk_register_clkdev(clks[clkidx], name, NULL); in cpg_mstp_clocks_init()
[all …]
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| D | clk-rz.c | 91 struct clk **clks; in rz_cpg_clocks_init() local
100 clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL); in rz_cpg_clocks_init()
101 BUG_ON(!cpg || !clks); in rz_cpg_clocks_init()
103 cpg->data.clks = clks; in rz_cpg_clocks_init()
119 cpg->data.clks[i] = clk; in rz_cpg_clocks_init()
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| /drivers/usb/host/ |
| D | ohci-st.c | 34 struct clk *clks[USB_MAX_CLKS]; member
70 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) { in st_ohci_platform_power_on()
71 ret = clk_prepare_enable(priv->clks[clk]); in st_ohci_platform_power_on()
90 clk_disable_unprepare(priv->clks[clk]); in st_ohci_platform_power_on()
115 if (priv->clks[clk]) in st_ohci_platform_power_off()
116 clk_disable_unprepare(priv->clks[clk]); in st_ohci_platform_power_off()
173 priv->clks[clk] = of_clk_get(dev->dev.of_node, clk); in st_ohci_platform_probe()
174 if (IS_ERR(priv->clks[clk])) { in st_ohci_platform_probe()
175 err = PTR_ERR(priv->clks[clk]); in st_ohci_platform_probe()
178 priv->clks[clk] = NULL; in st_ohci_platform_probe()
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| D | ehci-st.c | 35 struct clk *clks[USB_MAX_CLKS]; member
89 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) { in st_ehci_platform_power_on()
90 ret = clk_prepare_enable(priv->clks[clk]); in st_ehci_platform_power_on()
109 clk_disable_unprepare(priv->clks[clk]); in st_ehci_platform_power_on()
133 if (priv->clks[clk]) in st_ehci_platform_power_off()
134 clk_disable_unprepare(priv->clks[clk]); in st_ehci_platform_power_off()
191 priv->clks[clk] = of_clk_get(dev->dev.of_node, clk); in st_ehci_platform_probe()
192 if (IS_ERR(priv->clks[clk])) { in st_ehci_platform_probe()
193 err = PTR_ERR(priv->clks[clk]); in st_ehci_platform_probe()
196 priv->clks[clk] = NULL; in st_ehci_platform_probe()
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