Searched refs:clktrail (Results 1 – 3 of 3) sorted by relevance
28 timing->clktrail = 80; in mipi_dphy_timing_get_default()86 if (timing->clktrail < 60) in mipi_dphy_timing_validate()
28 unsigned int clktrail; member
390 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | in tegra_dsi_set_phy_timing()