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Searched refs:clock_type (Results 1 – 22 of 22) sorted by relevance

/drivers/nfc/fdp/
Di2c.c245 u8 *clock_type, u32 *clock_freq, in fdp_nci_i2c_read_device_properties() argument
251 r = device_property_read_u8(dev, FDP_DP_CLOCK_TYPE_NAME, clock_type); in fdp_nci_i2c_read_device_properties()
254 *clock_type = 0; in fdp_nci_i2c_read_device_properties()
291 *clock_type, *clock_freq, *fw_vsc_cfg != NULL ? "yes" : "no"); in fdp_nci_i2c_read_device_properties()
300 u8 clock_type; in fdp_nci_i2c_probe() local
345 fdp_nci_i2c_read_device_properties(dev, &clock_type, &clock_freq, in fdp_nci_i2c_probe()
351 clock_type, clock_freq, fw_vsc_cfg); in fdp_nci_i2c_probe()
Dfdp.c64 u8 clock_type; member
127 static int fdp_nci_set_clock(struct nci_dev *ndev, u8 clock_type, in fdp_nci_set_clock() argument
147 data[8] = clock_type; in fdp_nci_set_clock()
587 r = fdp_nci_set_clock(ndev, info->clock_type, info->clock_freq); in fdp_nci_post_setup()
744 int tx_tailroom, u8 clock_type, u32 clock_freq, in fdp_nci_probe() argument
761 info->clock_type = clock_type; in fdp_nci_probe()
Dfdp.h34 u8 clock_type, u32 clock_freq, u8 *fw_vsc_cfg);
/drivers/net/wan/
Dpci200syn.c129 switch(port->settings.clock_type) { in pci200_set_iface()
221 if (new_line.clock_type != CLOCK_EXT && in pci200_ioctl()
222 new_line.clock_type != CLOCK_TXFROMRX && in pci200_ioctl()
223 new_line.clock_type != CLOCK_INT && in pci200_ioctl()
224 new_line.clock_type != CLOCK_TXINT) in pci200_ioctl()
398 port->settings.clock_type = CLOCK_EXT; in pci200_pci_init_one()
Dc101.c158 switch(port->settings.clock_type) { in c101_set_iface()
265 if (new_line.clock_type != CLOCK_EXT && in c101_ioctl()
266 new_line.clock_type != CLOCK_TXFROMRX && in c101_ioctl()
267 new_line.clock_type != CLOCK_INT && in c101_ioctl()
268 new_line.clock_type != CLOCK_TXINT) in c101_ioctl()
380 card->settings.clock_type = CLOCK_EXT; in c101_run()
Dpc300too.c130 switch(port->settings.clock_type) { in pc300_set_iface()
246 if (new_line.clock_type != CLOCK_EXT && in pc300_ioctl()
247 new_line.clock_type != CLOCK_TXFROMRX && in pc300_ioctl()
248 new_line.clock_type != CLOCK_INT && in pc300_ioctl()
249 new_line.clock_type != CLOCK_TXINT) in pc300_ioctl()
459 port->settings.clock_type = CLOCK_EXT; in pc300_pci_init_one()
Dn2.c176 switch(port->settings.clock_type) { in n2_set_iface()
283 if (new_line.clock_type != CLOCK_EXT && in n2_ioctl()
284 new_line.clock_type != CLOCK_TXFROMRX && in n2_ioctl()
285 new_line.clock_type != CLOCK_INT && in n2_ioctl()
286 new_line.clock_type != CLOCK_TXINT) in n2_ioctl()
473 port->settings.clock_type = CLOCK_EXT; in n2_run()
Dwanxl.c62 unsigned int clock_type; member
359 line.clock_type = get_status(port)->clocking; in wanxl_ioctl()
377 if (line.clock_type != CLOCK_EXT && in wanxl_ioctl()
378 line.clock_type != CLOCK_TXFROMRX) in wanxl_ioctl()
384 get_status(port)->clocking = line.clock_type; in wanxl_ioctl()
Dixp4xx_hss.c266 unsigned int clock_type, clock_rate, loopback; member
403 if (port->clock_type == CLOCK_INT) in hss_config()
1265 new_line.clock_type = port->clock_type; in hss_hdlc_ioctl()
1279 clk = new_line.clock_type; in hss_hdlc_ioctl()
1289 port->clock_type = clk; /* Update settings */ in hss_hdlc_ioctl()
1355 port->clock_type = CLOCK_EXT; in hss_init_one()
Dfarsync.c1910 switch (sync.clock_type) { in fst_set_iface()
1969 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) == in fst_get_iface()
Dfsl_ucc_hdlc.c639 line.clock_type = priv->clocking; in uhdlc_ioctl()
Ddscc4.c998 if (settings->loopback && (settings->clock_type != CLOCK_INT)) { in dscc4_loopback_check()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_atombios.h156 u8 clock_type,
219 u8 clock_type,
Damdgpu_atombios.c982 u8 clock_type, in amdgpu_atombios_get_clock_dividers() argument
1003 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { in amdgpu_atombios_get_clock_dividers()
1004 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in amdgpu_atombios_get_clock_dividers()
1022 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in amdgpu_atombios_get_clock_dividers()
1052 args.v6_in.ulClock.ulComputeClockFlag = clock_type; in amdgpu_atombios_get_clock_dividers()
/drivers/video/fbdev/
Dsm501fb.c437 unsigned int clock_type; in sm501fb_set_par_common() local
448 clock_type = SM501_CLOCK_V2XCLK; in sm501fb_set_par_common()
454 clock_type = SM501_CLOCK_P2XCLK; in sm501fb_set_par_common()
461 clock_type = 0; in sm501fb_set_par_common()
507 sm501pixclock = sm501_set_clock(fbi->dev->parent, clock_type, in sm501fb_set_par_common()
/drivers/char/pcmcia/
Dsynclink_cs.c4117 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; in hdlcdev_ioctl()
4118 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; in hdlcdev_ioctl()
4119 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; in hdlcdev_ioctl()
4120 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; in hdlcdev_ioctl()
4121 default: new_line.clock_type = CLOCK_DEFAULT; in hdlcdev_ioctl()
4138 switch (new_line.clock_type) in hdlcdev_ioctl()
/drivers/staging/octeon-usb/
Docteon-hcd.c3540 const char *clock_type; in octeon_usb_probe() local
3575 "cavium,refclk-type", &clock_type); in octeon_usb_probe()
3578 "refclk-type", &clock_type); in octeon_usb_probe()
3580 if (!i && strcmp("crystal", clock_type) == 0) in octeon_usb_probe()
/drivers/gpu/drm/radeon/
Dradeon_atombios.c2825 u8 clock_type, in radeon_atom_get_clock_dividers() argument
2843 args.v1.ucAction = clock_type; in radeon_atom_get_clock_dividers()
2857 args.v2.ucAction = clock_type; in radeon_atom_get_clock_dividers()
2872 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { in radeon_atom_get_clock_dividers()
2873 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in radeon_atom_get_clock_dividers()
2891 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in radeon_atom_get_clock_dividers()
2922 args.v6_in.ulClock.ulComputeClockFlag = clock_type; in radeon_atom_get_clock_dividers()
Dradeon.h289 u8 clock_type,
/drivers/tty/
Dsynclinkmp.c1758 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; in hdlcdev_ioctl()
1759 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; in hdlcdev_ioctl()
1760 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; in hdlcdev_ioctl()
1761 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; in hdlcdev_ioctl()
1762 default: new_line.clock_type = CLOCK_DEFAULT; in hdlcdev_ioctl()
1779 switch (new_line.clock_type) in hdlcdev_ioctl()
Dsynclink_gt.c1642 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; in hdlcdev_ioctl()
1643 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; in hdlcdev_ioctl()
1644 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; in hdlcdev_ioctl()
1645 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; in hdlcdev_ioctl()
1646 default: new_line.clock_type = CLOCK_DEFAULT; in hdlcdev_ioctl()
1663 switch (new_line.clock_type) in hdlcdev_ioctl()
Dsynclink.c7844 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; in hdlcdev_ioctl()
7845 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; in hdlcdev_ioctl()
7846 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; in hdlcdev_ioctl()
7847 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; in hdlcdev_ioctl()
7848 default: new_line.clock_type = CLOCK_DEFAULT; in hdlcdev_ioctl()
7865 switch (new_line.clock_type) in hdlcdev_ioctl()