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Searched refs:contexts (Results 1 – 25 of 28) sorted by relevance

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/drivers/net/wireless/intel/iwlwifi/dvm/
Dmain.c629 priv->contexts[i].ctxid = i; in iwl_init_context()
631 priv->contexts[IWL_RXON_CTX_BSS].always_active = true; in iwl_init_context()
632 priv->contexts[IWL_RXON_CTX_BSS].is_active = true; in iwl_init_context()
633 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON; in iwl_init_context()
634 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING; in iwl_init_context()
635 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC; in iwl_init_context()
636 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM; in iwl_init_context()
637 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID; in iwl_init_context()
638 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY; in iwl_init_context()
639 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id = IWLAGN_BROADCAST_ID; in iwl_init_context()
[all …]
Drxon.c321 priv->contexts[IWL_RXON_CTX_BSS].vif && in iwl_send_rxon_timing()
322 priv->contexts[IWL_RXON_CTX_BSS].vif->bss_conf.beacon_int) { in iwl_send_rxon_timing()
324 priv->contexts[IWL_RXON_CTX_BSS].timing.beacon_interval; in iwl_send_rxon_timing()
328 priv->contexts[IWL_RXON_CTX_PAN].vif && in iwl_send_rxon_timing()
329 priv->contexts[IWL_RXON_CTX_PAN].vif->bss_conf.beacon_int && in iwl_send_rxon_timing()
333 priv->contexts[IWL_RXON_CTX_PAN].timing.beacon_interval; in iwl_send_rxon_timing()
407 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; in iwl_set_tx_power()
543 ctx_bss = &priv->contexts[IWL_RXON_CTX_BSS]; in iwlagn_set_pan_params()
544 ctx_pan = &priv->contexts[IWL_RXON_CTX_PAN]; in iwlagn_set_pan_params()
911 struct iwl_rxon_context *ctx = &priv->contexts[ctxid]; in iwl_print_rx_config_cmd()
Ddev.h742 struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX]; member
925 for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \
926 ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \
937 return iwl_is_associated_ctx(&priv->contexts[ctxid]); in iwl_is_associated()
Dmac80211.c355 if (priv->contexts[IWL_RXON_CTX_BSS].vif != vif) in iwlagn_mac_set_rekey_data()
375 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; in iwlagn_mac_suspend()
439 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; in iwlagn_mac_resume()
538 if (resume_data.valid && priv->contexts[IWL_RXON_CTX_BSS].vif) { in iwlagn_mac_resume()
978 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; in iwlagn_mac_channel_switch()
1052 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; in iwl_chswitch_done()
Ddevices.c409 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; in iwl5000_hw_channel_switch()
570 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; in iwl6000_hw_channel_switch()
Dscan.c639 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; in iwlagn_request_scan()
760 priv->contexts[IWL_RXON_CTX_BSS].active.flags & in iwlagn_request_scan()
Drx.c71 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; in iwlagn_rx_csa()
584 if (priv->contexts[IWL_RXON_CTX_BSS].active.filter_flags & in iwlagn_set_decrypted_flag()
Dlib.c604 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; in iwlagn_fill_txpower_mode()
1062 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; in iwlagn_suspend()
Dtx.c286 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; in iwlagn_tx_skb()
775 vif = priv->contexts[ctx].vif; in iwlagn_check_ratid_empty()
Dcalib.c970 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; in iwl_chain_noise_calibration()
/drivers/gpu/drm/nouveau/
Dnv84_fence.c178 priv->suspend = vmalloc(priv->base.contexts * sizeof(u32)); in nv84_fence_suspend()
180 for (i = 0; i < priv->base.contexts; i++) in nv84_fence_suspend()
194 for (i = 0; i < priv->base.contexts; i++) in nv84_fence_resume()
235 priv->base.contexts = fifo->nr; in nv84_fence_create()
236 priv->base.context_base = fence_context_alloc(priv->base.contexts); in nv84_fence_create()
248 ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, domain, 0, in nv84_fence_create()
262 ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, in nv84_fence_create()
Dnv04_fence.c112 priv->base.contexts = 15; in nv04_fence_create()
113 priv->base.context_base = fence_context_alloc(priv->base.contexts); in nv04_fence_create()
Dnv10_fence.c109 priv->base.contexts = 31; in nv10_fence_create()
110 priv->base.context_base = fence_context_alloc(priv->base.contexts); in nv10_fence_create()
Dnv50_fence.c99 priv->base.contexts = 127; in nv50_fence_create()
100 priv->base.context_base = fence_context_alloc(priv->base.contexts); in nv50_fence_create()
Dnv17_fence.c128 priv->base.contexts = 31; in nv17_fence_create()
129 priv->base.context_base = fence_context_alloc(priv->base.contexts); in nv17_fence_create()
Dnouveau_fence.h60 u32 contexts; member
Dnouveau_fence.c85 fence->context >= priv->context_base + priv->contexts) in nouveau_local_fence()
/drivers/staging/media/omap4iss/
Diss_csi2.c258 struct iss_csi2_ctx_cfg *ctx = &csi2->contexts[0]; in csi2_set_outaddr()
287 struct iss_csi2_ctx_cfg *ctx = &csi2->contexts[ctxnum]; in csi2_ctx_enable()
542 if (csi2->contexts[0].enabled || csi2->ctrl.if_enable) in csi2_configure()
572 csi2->contexts[0].format_id = csi2_ctx_map_format(csi2); in csi2_configure()
575 csi2->contexts[0].data_offset = 0; in csi2_configure()
577 csi2->contexts[0].data_offset = csi2->video_out.bpl_value; in csi2_configure()
586 csi2->contexts[0].eof_enabled = 1; in csi2_configure()
587 csi2->contexts[0].eol_enabled = 1; in csi2_configure()
596 csi2_ctx_config(csi2, &csi2->contexts[0]); in csi2_configure()
784 csi2_isr_ctx(csi2, &csi2->contexts[0]); in omap4iss_csi2_isr()
Diss_csi2.h143 struct iss_csi2_ctx_cfg contexts[ISS_CSI2_MAX_CTX_NUM + 1]; member
/drivers/media/platform/omap3isp/
Dispcsi2.c223 struct isp_csi2_ctx_cfg *ctx = &csi2->contexts[0]; in csi2_set_outaddr()
253 struct isp_csi2_ctx_cfg *ctx = &csi2->contexts[ctxnum]; in csi2_ctx_enable()
564 if (csi2->contexts[0].enabled || csi2->ctrl.if_enable) in csi2_configure()
600 csi2->contexts[0].format_id = csi2_ctx_map_format(csi2); in csi2_configure()
603 csi2->contexts[0].data_offset = 0; in csi2_configure()
605 csi2->contexts[0].data_offset = csi2->video_out.bpl_value; in csi2_configure()
614 csi2->contexts[0].eof_enabled = 1; in csi2_configure()
615 csi2->contexts[0].eol_enabled = 1; in csi2_configure()
624 csi2_ctx_config(isp, csi2, &csi2->contexts[0]); in csi2_configure()
791 csi2_isr_ctx(csi2, &csi2->contexts[0]); in omap3isp_csi2_isr()
Dispcsi2.h140 struct isp_csi2_ctx_cfg contexts[ISP_CSI2_MAX_CTX_NUM + 1]; member
/drivers/gpu/drm/tegra/
Ddrm.c27 struct list_head contexts; member
249 INIT_LIST_HEAD(&fpriv->contexts); in tegra_drm_open()
438 list_for_each_entry(ctx, &file->contexts, list) in tegra_drm_file_owns_context()
543 list_add(&context->list, &fpriv->contexts); in tegra_open_channel()
862 list_for_each_entry_safe(context, tmp, &fpriv->contexts, list) in tegra_drm_preclose()
/drivers/staging/speakup/
DTODO20 are called in various contexts, and a couple of things can't happen
/drivers/gpu/drm/
Ddrm_ioc32.c635 u32 contexts; member
653 || __put_user((struct drm_ctx __user *) (unsigned long)res32.contexts, in compat_drm_resctx()
654 &res->contexts)) in compat_drm_resctx()
Ddrm_context.c339 if (copy_to_user(&res->contexts[i], &ctx, sizeof(ctx))) in drm_legacy_resctx()

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