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Searched refs:crtc1 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dnv04.c52 u32 crtc1 = nvkm_rd32(device, 0x602100); in nv04_disp_intr() local
60 if (crtc1 & 0x00000001) { in nv04_disp_intr()
/drivers/video/fbdev/matrox/
Dmatroxfb_base.c181 if (minfo->crtc1.panpos >= 0) { in matroxfb_crtc1_panpos()
186 panpos = minfo->crtc1.panpos; in matroxfb_crtc1_panpos()
190 minfo->crtc1.panpos = -1; /* No update pending anymore */ in matroxfb_crtc1_panpos()
211 minfo->crtc1.vsync.cnt++; in matrox_irq()
213 wake_up_interruptible(&minfo->crtc1.vsync.wait); in matrox_irq()
276 vs = &minfo->crtc1.vsync; in matroxfb_wait_for_sync()
342 minfo->crtc1.panpos = p2; in matrox_pan_var()
345 minfo->crtc1.panpos = -1; in matrox_pan_var()
807 minfo->crtc1.pixclock = mt.pixclock; in matroxfb_set_par()
808 minfo->crtc1.mnp = mt.mnp; in matroxfb_set_par()
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Dmatroxfb_DAC1064.c175 pixelmnp = minfo->crtc1.mnp; in g450_set_plls()
211 pxc = minfo->crtc1.pixclock; in g450_set_plls()
1056 minfo->crtc1.panpos = -1; in MGA1064_restore()
1082 minfo->crtc1.panpos = -1; in MGAG100_restore()
Dmatroxfb_base.h361 } crtc1; member
Dmatroxfb_Ti3026.c583 minfo->crtc1.panpos = -1; in Ti3026_restore()
/drivers/gpu/drm/radeon/
Devergreen.c4613 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; in evergreen_irq_set() local
4697 crtc1 |= VBLANK_INT_MASK; in evergreen_irq_set()
4787 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in evergreen_irq_set()
Dsi.c6074 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; in si_irq_set() local
6135 crtc1 |= VBLANK_INT_MASK; in si_irq_set()
6202 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in si_irq_set()
Dcik.c7091 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; in cik_irq_set() local
7175 crtc1 |= VBLANK_INTERRUPT_MASK; in cik_irq_set()
7236 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in cik_irq_set()