| /drivers/gpu/drm/omapdrm/ |
| D | omap_drv.c | 66 u32 crtcs; member
112 priv->commit.pending &= ~commit->crtcs; in omap_atomic_complete()
134 pending = priv->commit.pending & commit->crtcs; in omap_atomic_is_pending()
168 commit->crtcs |= drm_crtc_mask(crtc); in omap_atomic_commit()
173 priv->commit.pending |= commit->crtcs; in omap_atomic_commit()
218 struct drm_crtc *crtc = priv->crtcs[i]; in channel_used()
281 BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs)); in omap_modeset_create_crtc()
282 priv->crtcs[id] = crtc; in omap_modeset_create_crtc()
463 struct drm_crtc *crtc = priv->crtcs[id]; in omap_modeset_init()
687 drm_crtc_vblank_off(priv->crtcs[i]); in dev_load()
[all …]
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| D | omap_irq.c | 150 struct drm_crtc *crtc = priv->crtcs[pipe]; in omap_irq_enable_vblank()
175 struct drm_crtc *crtc = priv->crtcs[pipe]; in omap_irq_disable_vblank()
202 struct drm_crtc *crtc = priv->crtcs[id]; in omap_irq_handler()
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| /drivers/gpu/drm/ |
| D | drm_atomic.c | 62 kfree(state->crtcs); in drm_atomic_state_default_release()
83 state->crtcs = kcalloc(dev->mode_config.num_crtc, in drm_atomic_state_init()
84 sizeof(*state->crtcs), GFP_KERNEL); in drm_atomic_state_init()
85 if (!state->crtcs) in drm_atomic_state_init()
159 struct drm_crtc *crtc = state->crtcs[i].ptr; in drm_atomic_state_default_clear()
165 state->crtcs[i].state); in drm_atomic_state_default_clear()
167 if (state->crtcs[i].commit) { in drm_atomic_state_default_clear()
168 kfree(state->crtcs[i].commit->event); in drm_atomic_state_default_clear()
169 state->crtcs[i].commit->event = NULL; in drm_atomic_state_default_clear()
170 drm_crtc_commit_put(state->crtcs[i].commit); in drm_atomic_state_default_clear()
[all …]
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| D | drm_fb_helper.c | 2035 struct drm_fb_helper_crtc **crtcs, *crtc; in drm_pick_crtcs() local
2049 crtcs = kzalloc(fb_helper->connector_count * in drm_pick_crtcs()
2051 if (!crtcs) in drm_pick_crtcs()
2099 crtcs[n] = crtc; in drm_pick_crtcs()
2100 memcpy(crtcs, best_crtcs, n * sizeof(struct drm_fb_helper_crtc *)); in drm_pick_crtcs()
2101 score = my_score + drm_pick_crtcs(fb_helper, crtcs, modes, n + 1, in drm_pick_crtcs()
2105 memcpy(best_crtcs, crtcs, in drm_pick_crtcs()
2111 kfree(crtcs); in drm_pick_crtcs()
2118 struct drm_fb_helper_crtc **crtcs; in drm_setup_crtcs() local
2130 crtcs = kcalloc(fb_helper->connector_count, in drm_setup_crtcs()
[all …]
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| D | drm_atomic_helper.c | 1456 state->crtcs[i].commit = commit; in drm_atomic_helper_setup_commit()
1583 commit = state->crtcs[i].commit; in drm_atomic_helper_commit_hw_done()
1616 commit = state->crtcs[i].commit; in drm_atomic_helper_commit_cleanup_done()
2044 swap(state->crtcs[i].state, crtc->state); in drm_atomic_helper_swap_state()
2047 if (state->crtcs[i].commit) { in drm_atomic_helper_swap_state()
2049 list_add(&state->crtcs[i].commit->commit_entry, in drm_atomic_helper_swap_state()
2053 state->crtcs[i].commit->event = NULL; in drm_atomic_helper_swap_state()
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| /drivers/gpu/drm/exynos/ |
| D | exynos_drm_drv.c | 45 u32 crtcs; member
75 priv->pending &= ~commit->crtcs; in exynos_atomic_commit_complete()
207 static int commit_is_pending(struct exynos_drm_private *priv, u32 crtcs) in commit_is_pending() argument
212 pending = priv->pending & crtcs; in commit_is_pending()
247 commit->crtcs |= drm_crtc_mask(crtc); in exynos_atomic_commit()
249 wait_event(priv->wait, !commit_is_pending(priv, commit->crtcs)); in exynos_atomic_commit()
252 priv->pending |= commit->crtcs; in exynos_atomic_commit()
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| /drivers/gpu/drm/rcar-du/ |
| D | rcar_du_group.c | 217 ret = clk_prepare_enable(rcdu->crtcs[0].clock); in rcar_du_set_dpad0_vsp1_routing()
223 clk_disable_unprepare(rcdu->crtcs[0].clock); in rcar_du_set_dpad0_vsp1_routing()
230 struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2]; in rcar_du_group_set_routing()
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| D | rcar_du_kms.c | 256 u32 crtcs; member
279 rcdu->commit.pending &= ~commit->crtcs; in rcar_du_atomic_complete()
324 commit->crtcs |= drm_crtc_mask(crtc); in rcar_du_atomic_commit()
328 !(rcdu->commit.pending & commit->crtcs)); in rcar_du_atomic_commit()
330 rcdu->commit.pending |= commit->crtcs; in rcar_du_atomic_commit()
613 rcdu->crtcs[i].vsp = vsp; in rcar_du_modeset_init()
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| D | rcar_du_drv.c | 187 rcar_du_crtc_enable_vblank(&rcdu->crtcs[pipe], true); in rcar_du_enable_vblank()
196 rcar_du_crtc_enable_vblank(&rcdu->crtcs[pipe], false); in rcar_du_disable_vblank()
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| D | rcar_du_drv.h | 86 struct rcar_du_crtc crtcs[RCAR_DU_MAX_CRTCS]; member
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| D | rcar_du_plane.c | 725 unsigned int crtcs; in rcar_du_planes_init() local
734 crtcs = ((1 << rcdu->num_crtcs) - 1) & (3 << (2 * rgrp->index)); in rcar_du_planes_init()
744 ret = drm_universal_plane_init(rcdu->ddev, &plane->plane, crtcs, in rcar_du_planes_init()
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| /drivers/gpu/drm/msm/mdp/mdp5/ |
| D | mdp5_kms.c | 324 static const enum mdp5_pipe crtcs[] = { in modeset_init() enum
345 plane = mdp5_plane_init(dev, crtcs[i], true, in modeset_init()
350 pipe2name(crtcs[i]), ret); in modeset_init()
358 pipe2name(crtcs[i]), ret); in modeset_init()
361 priv->crtcs[priv->num_crtcs++] = crtc; in modeset_init()
462 crtc = priv->crtcs[pipe]; in mdp5_get_scanoutpos()
529 crtc = priv->crtcs[pipe]; in mdp5_get_vblank_timestamp()
549 crtc = priv->crtcs[pipe]; in mdp5_get_vblank_counter()
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| D | mdp5_irq.c | 90 if (status & mdp5_crtc_vblank(priv->crtcs[id])) in mdp5_irq()
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| /drivers/gpu/drm/radeon/ |
| D | rs690.c | 252 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in rs690_line_buffer_adjust()
255 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in rs690_line_buffer_adjust()
598 if (rdev->mode_info.crtcs[0]->base.enabled) in rs690_bandwidth_update()
599 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs690_bandwidth_update()
600 if (rdev->mode_info.crtcs[1]->base.enabled) in rs690_bandwidth_update()
601 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs690_bandwidth_update()
625 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); in rs690_bandwidth_update()
626 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); in rs690_bandwidth_update()
628 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true); in rs690_bandwidth_update()
629 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true); in rs690_bandwidth_update()
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| D | rv515.c | 1243 if (rdev->mode_info.crtcs[0]->base.enabled) in rv515_bandwidth_avivo_update()
1244 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_avivo_update()
1245 if (rdev->mode_info.crtcs[1]->base.enabled) in rv515_bandwidth_avivo_update()
1246 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rv515_bandwidth_avivo_update()
1249 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); in rv515_bandwidth_avivo_update()
1250 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); in rv515_bandwidth_avivo_update()
1252 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); in rv515_bandwidth_avivo_update()
1253 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); in rv515_bandwidth_avivo_update()
1285 if (rdev->mode_info.crtcs[0]->base.enabled) in rv515_bandwidth_update()
1286 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_update()
[all …]
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| D | rs600.c | 115 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip()
146 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip_pending()
900 if (rdev->mode_info.crtcs[0]->base.enabled) in rs600_bandwidth_update()
901 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs600_bandwidth_update()
902 if (rdev->mode_info.crtcs[1]->base.enabled) in rs600_bandwidth_update()
903 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs600_bandwidth_update()
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| D | radeon_kms.c | 255 crtc = (struct drm_crtc *)minfo->crtcs[i]; in radeon_info_ioctl()
783 if (rdev->mode_info.crtcs[pipe]) { in radeon_get_vblank_counter_kms()
796 &rdev->mode_info.crtcs[pipe]->base.hwmode); in radeon_get_vblank_counter_kms()
902 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; in radeon_get_vblank_timestamp_kms()
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| D | radeon_display.c | 290 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_vblank()
346 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && in radeon_crtc_handle_vblank()
371 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_flip()
418 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; in radeon_flip_work_func()
694 rdev->mode_info.crtcs[index] = radeon_crtc; in radeon_crtc_init()
1981 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; in radeon_get_crtc_scanoutpos()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | dce_v6_0.c | 219 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_page_flip()
1287 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v6_0_bandwidth_update()
1291 mode0 = &adev->mode_info.crtcs[i]->base.mode; in dce_v6_0_bandwidth_update()
1292 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; in dce_v6_0_bandwidth_update()
1293 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); in dce_v6_0_bandwidth_update()
1294 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1295 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); in dce_v6_0_bandwidth_update()
1296 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); in dce_v6_0_bandwidth_update()
2179 if (adev->mode_info.crtcs[i] && in dce_v6_0_crtc_disable()
2180 adev->mode_info.crtcs[i]->enabled && in dce_v6_0_crtc_disable()
[all …]
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| D | amdgpu_kms.c | 248 crtc = (struct drm_crtc *)minfo->crtcs[i]; in amdgpu_info_ioctl()
655 if (adev->mode_info.crtcs[pipe]) { in amdgpu_get_vblank_counter_kms()
668 &adev->mode_info.crtcs[pipe]->base.hwmode); in amdgpu_get_vblank_counter_kms()
754 crtc = &adev->mode_info.crtcs[pipe]->base; in amdgpu_get_vblank_timestamp_kms()
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| D | dce_v8_0.c | 240 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v8_0_page_flip()
1345 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v8_0_bandwidth_update()
1349 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v8_0_bandwidth_update()
1350 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v8_0_bandwidth_update()
1351 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v8_0_bandwidth_update()
2711 if (adev->mode_info.crtcs[i] && in dce_v8_0_crtc_disable()
2712 adev->mode_info.crtcs[i]->enabled && in dce_v8_0_crtc_disable()
2714 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v8_0_crtc_disable()
2843 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v8_0_crtc_init()
3353 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v8_0_pageflip_irq()
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| /drivers/gpu/drm/arm/ |
| D | malidp_planes.c | 220 unsigned long crtcs = 1 << drm->mode_config.num_crtc; in malidp_de_planes_init() local
247 ret = drm_universal_plane_init(drm, &plane->base, crtcs, in malidp_de_planes_init()
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| /drivers/gpu/drm/msm/mdp/mdp4/ |
| D | mdp4_irq.c | 85 if (status & mdp4_crtc_vblank(priv->crtcs[id])) in mdp4_irq()
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| /drivers/gpu/drm/i915/ |
| D | intel_fbdev.c | 357 struct drm_fb_helper_crtc **crtcs, in intel_fb_initial_config() argument
443 if (crtcs[j] == new_crtc) { in intel_fb_initial_config()
491 crtcs[i] = new_crtc; in intel_fb_initial_config()
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| /drivers/gpu/drm/i2c/ |
| D | tda998x_drv.c | 1615 u32 crtcs = 0; in tda998x_bind() local
1625 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); in tda998x_bind()
1628 if (crtcs == 0) { in tda998x_bind()
1630 crtcs = 1 << 0; in tda998x_bind()
1634 priv->encoder.possible_crtcs = crtcs; in tda998x_bind()
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