| /drivers/char/hw_random/ |
| D | xgene-rng.c | 93 void __iomem *csr_base; member
127 writel(fro_val, ctx->csr_base + RNG_FRODETUNE); in xgene_rng_init_fro()
128 writel(0x00000000, ctx->csr_base + RNG_ALARMMASK); in xgene_rng_init_fro()
129 writel(0x00000000, ctx->csr_base + RNG_ALARMSTOP); in xgene_rng_init_fro()
130 writel(0xFFFFFFFF, ctx->csr_base + RNG_FROENABLE); in xgene_rng_init_fro()
137 val = readl(ctx->csr_base + RNG_INTR_STS_ACK); in xgene_rng_chk_overflow()
183 frostopped = readl(ctx->csr_base + RNG_ALARMSTOP); in xgene_rng_chk_overflow()
208 frostopped = readl(ctx->csr_base + RNG_ALARMSTOP); in xgene_rng_chk_overflow()
213 writel(val, ctx->csr_base + RNG_INTR_STS_ACK); in xgene_rng_chk_overflow()
232 val = readl(ctx->csr_base + RNG_INTR_STS_ACK); in xgene_rng_data_present()
[all …]
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| /drivers/rtc/ |
| D | rtc-xgene.c | 52 void __iomem *csr_base; member
61 rtc_time_to_tm(readl(pdata->csr_base + RTC_CCVR), tm); in xgene_rtc_read_time()
73 writel((u32) secs, pdata->csr_base + RTC_CLR); in xgene_rtc_set_mmss()
74 readl(pdata->csr_base + RTC_CLR); /* Force a barrier */ in xgene_rtc_set_mmss()
84 alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE; in xgene_rtc_read_alarm()
94 ccr = readl(pdata->csr_base + RTC_CCR); in xgene_rtc_alarm_irq_enable()
102 writel(ccr, pdata->csr_base + RTC_CCR); in xgene_rtc_alarm_irq_enable()
113 rtc_time = readl(pdata->csr_base + RTC_CCVR); in xgene_rtc_set_alarm()
117 writel((u32) pdata->alarm_time, pdata->csr_base + RTC_CMR); in xgene_rtc_set_alarm()
137 if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT)) in xgene_rtc_interrupt()
[all …]
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| /drivers/mtd/maps/ |
| D | intel_vr_nor.c | 43 void __iomem *csr_base; member
103 exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0); in vr_nor_destroy_maps()
105 writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0); in vr_nor_destroy_maps()
111 iounmap(p->csr_base); in vr_nor_destroy_maps()
136 p->csr_base = ioremap_nocache(csr_phys, csr_len); in vr_nor_init_maps()
137 if (!p->csr_base) in vr_nor_init_maps()
140 exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0); in vr_nor_init_maps()
164 writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0); in vr_nor_init_maps()
169 iounmap(p->csr_base); in vr_nor_init_maps()
232 exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0); in vr_nor_pci_probe()
[all …]
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| /drivers/mtd/nand/ |
| D | denali_pci.c | 34 resource_size_t csr_base, mem_base; in denali_pci_probe() local
52 csr_base = pci_resource_start(dev, 1); in denali_pci_probe()
56 csr_base = pci_resource_start(dev, 0); in denali_pci_probe()
61 mem_base = csr_base + csr_len; in denali_pci_probe()
76 denali->flash_reg = ioremap_nocache(csr_base, csr_len); in denali_pci_probe()
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| /drivers/pci/host/ |
| D | pcie-altera-msi.c | 44 void __iomem *csr_base; member
54 writel_relaxed(value, msi->csr_base + reg); in msi_writel()
59 return readl_relaxed(msi->csr_base + reg); in msi_readl()
244 msi->csr_base = devm_ioremap_resource(&pdev->dev, res); in altera_msi_probe()
245 if (IS_ERR(msi->csr_base)) { in altera_msi_probe()
247 return PTR_ERR(msi->csr_base); in altera_msi_probe()
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| D | pci-xgene.c | 72 void __iomem *csr_base; member
81 return readl(port->csr_base + reg); in xgene_pcie_readl()
86 writel(val, port->csr_base + reg); in xgene_pcie_writel()
260 port->csr_base = devm_ioremap_resource(dev, res); in xgene_pcie_map_reg()
261 if (IS_ERR(port->csr_base)) in xgene_pcie_map_reg()
262 return PTR_ERR(port->csr_base); in xgene_pcie_map_reg()
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| /drivers/crypto/qat/qat_common/ |
| D | adf_accel_devices.h | 198 #define ADF_CSR_WR(csr_base, csr_offset, val) \ argument
199 __raw_writel(val, csr_base + csr_offset)
202 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset) argument
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| /drivers/net/phy/ |
| D | mdio-xgene.c | 348 void __iomem *csr_base; in xgene_mdio_probe() local
374 csr_base = devm_ioremap_resource(dev, res); in xgene_mdio_probe()
375 if (IS_ERR(csr_base)) in xgene_mdio_probe()
376 return PTR_ERR(csr_base); in xgene_mdio_probe()
377 pdata->mac_csr_addr = csr_base; in xgene_mdio_probe()
378 pdata->mdio_csr_addr = csr_base + BLOCK_XG_MDIO_CSR_OFFSET; in xgene_mdio_probe()
379 pdata->diag_csr_addr = csr_base + BLOCK_DIAG_CSR_OFFSET; in xgene_mdio_probe()
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| /drivers/ata/ |
| D | sata_fsl.c | 287 void __iomem *csr_base; member
358 void __iomem *csr_base = host_priv->csr_base; in fsl_sata_rx_watermark_show() local
361 rx_watermark = ioread32(csr_base + TRANSCFG); in fsl_sata_rx_watermark_show()
376 void __iomem *csr_base = host_priv->csr_base; in fsl_sata_rx_watermark_store() local
385 temp = ioread32(csr_base + TRANSCFG); in fsl_sata_rx_watermark_store()
387 iowrite32(temp | rx_watermark, csr_base + TRANSCFG); in fsl_sata_rx_watermark_store()
588 ioread32(COMMANDSTAT + host_priv->csr_base)); in sata_fsl_qc_issue()
666 ioread32(host_priv->csr_base + COMMANDSTAT)); in sata_fsl_freeze()
1457 void __iomem *csr_base = NULL; in sata_fsl_probe() local
1473 csr_base = hcr_base + 0x140; in sata_fsl_probe()
[all …]
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| /drivers/net/wan/lmc/ |
| D | lmc_main.c | 98 static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, size_t csr_size);
2040 static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, /*fold00*/ in lmc_initcsrs() argument
2044 sc->lmc_csrs.csr_busmode = csr_base + 0 * csr_size; in lmc_initcsrs()
2045 sc->lmc_csrs.csr_txpoll = csr_base + 1 * csr_size; in lmc_initcsrs()
2046 sc->lmc_csrs.csr_rxpoll = csr_base + 2 * csr_size; in lmc_initcsrs()
2047 sc->lmc_csrs.csr_rxlist = csr_base + 3 * csr_size; in lmc_initcsrs()
2048 sc->lmc_csrs.csr_txlist = csr_base + 4 * csr_size; in lmc_initcsrs()
2049 sc->lmc_csrs.csr_status = csr_base + 5 * csr_size; in lmc_initcsrs()
2050 sc->lmc_csrs.csr_command = csr_base + 6 * csr_size; in lmc_initcsrs()
2051 sc->lmc_csrs.csr_intr = csr_base + 7 * csr_size; in lmc_initcsrs()
[all …]
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| /drivers/phy/ |
| D | phy-xgene.c | 562 static void sds_wr(void __iomem *csr_base, u32 indirect_cmd_reg, in sds_wr() argument
571 writel(data, csr_base + indirect_data_reg); in sds_wr()
572 readl(csr_base + indirect_data_reg); /* Force a barrier */ in sds_wr()
573 writel(cmd, csr_base + indirect_cmd_reg); in sds_wr()
574 readl(csr_base + indirect_cmd_reg); /* Force a barrier */ in sds_wr()
576 val = readl(csr_base + indirect_cmd_reg); in sds_wr()
581 csr_base + indirect_cmd_reg, addr, data); in sds_wr()
584 static void sds_rd(void __iomem *csr_base, u32 indirect_cmd_reg, in sds_rd() argument
593 writel(cmd, csr_base + indirect_cmd_reg); in sds_rd()
594 readl(csr_base + indirect_cmd_reg); /* Force a barrier */ in sds_rd()
[all …]
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| /drivers/block/ |
| D | umem.c | 796 unsigned long csr_base; in mm_pci_probe() local
813 csr_base = pci_resource_start(dev, 0); in mm_pci_probe()
815 if (!csr_base || !csr_len) in mm_pci_probe()
834 card->csr_remap = ioremap_nocache(csr_base, csr_len); in mm_pci_probe()
845 csr_base, card->csr_remap, csr_len); in mm_pci_probe()
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