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Searched refs:enable_bit (Results 1 – 25 of 33) sorted by relevance

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/drivers/clk/sirf/
Dclk-common.c43 signed char enable_bit; /* enable bit: 0 ~ 63 */ member
51 signed char enable_bit; /* enable bit: 0 ~ 63 */ member
536 .enable_bit = 0,
551 .enable_bit = 8,
566 .enable_bit = 9,
586 .enable_bit = 10,
601 .enable_bit = 11,
638 bit = clk->enable_bit % 32; in std_clk_is_enabled()
639 reg = clk->enable_bit / 32; in std_clk_is_enabled()
651 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); in std_clk_enable()
[all …]
Dclk-atlas6.c23 .enable_bit = 59,
31 .enable_bit = 60,
39 .enable_bit = 61,
54 .enable_bit = 34,
Dclk-prima2.c23 .enable_bit = 59,
31 .enable_bit = 60,
39 .enable_bit = 61,
53 .enable_bit = 34,
/drivers/clk/ti/
Dclkt_dflt.c153 *other_bit = clk->enable_bit; in omap2_clk_dflt_find_companion()
178 *idlest_bit = clk->enable_bit; in omap2_clk_dflt_find_idlest()
235 v &= ~(1 << clk->enable_bit); in omap2_dflt_clk_enable()
237 v |= (1 << clk->enable_bit); in omap2_dflt_clk_enable()
279 v |= (1 << clk->enable_bit); in omap2_dflt_clk_disable()
281 v &= ~(1 << clk->enable_bit); in omap2_dflt_clk_disable()
306 v ^= BIT(clk->enable_bit); in omap2_dflt_clk_is_enabled()
308 v &= BIT(clk->enable_bit); in omap2_dflt_clk_is_enabled()
Dclkt_iclk.c40 v |= (1 << clk->enable_bit); in omap2_clkt_iclk_allow_idle()
54 v &= ~(1 << clk->enable_bit); in omap2_clkt_iclk_deny_idle()
79 *idlest_bit = clk->enable_bit; in omap2430_clk_i2chs_find_idlest()
Dgate.c113 clk_hw->enable_bit = bit_idx; in _register_gate()
197 gate->enable_bit = setup->bit_shift; in ti_clk_build_component_gate()
219 u8 enable_bit = 0; in _of_ti_gate_clk_setup() local
230 enable_bit = val; in _of_ti_gate_clk_setup()
247 enable_bit, clk_gate_flags, ops, hw_ops); in _of_ti_gate_clk_setup()
270 gate->enable_bit = val; in _of_ti_composite_gate_clk_setup()
Dinterface.c52 clk_hw->enable_bit = bit_idx; in _register_interface()
110 u8 enable_bit = 0; in _of_ti_interface_clk_setup() local
118 enable_bit = val; in _of_ti_interface_clk_setup()
127 enable_bit, ops); in _of_ti_interface_clk_setup()
Dclk-3xxx.c162 *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; in am35xx_clk_find_idlest()
185 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) in am35xx_clk_find_companion()
186 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
188 *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
/drivers/regulator/
Dtps6586x-regulator.c62 int enable_bit[2]; member
131 .enable_bit[0] = (ebit0), \
133 .enable_bit[1] = (ebit1),
156 .enable_bit[0] = (ebit0), \
158 .enable_bit[1] = (ebit1),
277 ri->enable_bit[0] == ri->enable_bit[1]) in tps6586x_regulator_preinit()
288 if (!(val2 & (1 << ri->enable_bit[1]))) in tps6586x_regulator_preinit()
295 if (!(val1 & (1 << ri->enable_bit[0]))) { in tps6586x_regulator_preinit()
297 1 << ri->enable_bit[0]); in tps6586x_regulator_preinit()
303 1 << ri->enable_bit[1]); in tps6586x_regulator_preinit()
Dmc13xxx.h20 int enable_bit; member
71 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
89 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
104 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
Dmc13xxx-regulator-core.c40 mc13xxx_regulators[id].enable_bit, in mc13xxx_regulator_enable()
41 mc13xxx_regulators[id].enable_bit); in mc13xxx_regulator_enable()
53 mc13xxx_regulators[id].enable_bit, 0); in mc13xxx_regulator_disable()
67 return (val & mc13xxx_regulators[id].enable_bit) != 0; in mc13xxx_regulator_is_enabled()
Dmc13783-regulator.c334 u32 en_val = mc13xxx_regulators[id].enable_bit; in mc13783_gpo_regulator_enable()
343 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, in mc13783_gpo_regulator_enable()
359 dis_val = mc13xxx_regulators[id].enable_bit; in mc13783_gpo_regulator_disable()
361 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, in mc13783_gpo_regulator_disable()
384 return (val & mc13xxx_regulators[id].enable_bit) != 0; in mc13783_gpo_regulator_is_enabled()
Dda903x.c86 int enable_bit; member
145 1 << info->enable_bit); in da903x_enable()
154 1 << info->enable_bit); in da903x_disable()
168 return !!(reg_val & (1 << info->enable_bit)); in da903x_is_enabled()
330 .enable_bit = (ebit), \
352 .enable_bit = (ebit), \
Dmc13892-regulator.c341 u32 en_val = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_enable()
342 u32 mask = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_enable()
366 dis_val = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_disable()
368 return mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit, in mc13892_gpo_regulator_disable()
390 return (val & mc13892_regulators[id].enable_bit) != 0; in mc13892_gpo_regulator_is_enabled()
/drivers/watchdog/
DiTCO_wdt.c150 u32 enable_bit; in no_reboot_bit() local
155 enable_bit = 0x00000010; in no_reboot_bit()
158 enable_bit = 0x00000020; in no_reboot_bit()
163 enable_bit = 0x00000002; in no_reboot_bit()
167 return enable_bit; in no_reboot_bit()
188 u32 enable_bit = no_reboot_bit(); in iTCO_wdt_unset_NO_REBOOT_bit() local
194 val32 &= ~enable_bit; in iTCO_wdt_unset_NO_REBOOT_bit()
200 val32 &= ~enable_bit; in iTCO_wdt_unset_NO_REBOOT_bit()
206 if (val32 & enable_bit) in iTCO_wdt_unset_NO_REBOOT_bit()
/drivers/clk/renesas/
Dclk-sh73a0.c94 u32 enable_bit = name[3] - '0'; in sh73a0_cpg_register_clock() local
97 switch (enable_bit) { in sh73a0_cpg_register_clock()
113 if (clk_readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
116 if (enable_bit == 1 || enable_bit == 2) in sh73a0_cpg_register_clock()
/drivers/sh/clk/
Dcpg.c56 sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); in sh_clk_mstp_enable()
71 (read(mapped_status) & (1 << clk->enable_bit)) && i; in sh_clk_mstp_enable()
76 clk->enable_reg, clk->enable_bit); in sh_clk_mstp_enable()
85 sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); in sh_clk_mstp_disable()
138 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()
154 value &= ~(clk->div_mask << clk->enable_bit); in sh_clk_div_set_rate()
155 value |= (idx << clk->enable_bit); in sh_clk_div_set_rate()
/drivers/clk/ingenic/
Djz4740-cgu.c84 .enable_bit = 8,
281 cppcr &= ~BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit); in jz4740_clock_suspend()
290 cppcr |= BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit); in jz4740_clock_resume()
Dcgu.h59 u8 enable_bit; member
/drivers/perf/
Dxgene_pmu.c1004 int enable_bit; in acpi_get_pmu_hw_inf() local
1030 enable_bit = 0; in acpi_get_pmu_hw_inf()
1032 enable_bit = (int) obj->integer.value; in acpi_get_pmu_hw_inf()
1034 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit); in acpi_get_pmu_hw_inf()
1042 inf->enable_mask = 1 << enable_bit; in acpi_get_pmu_hw_inf()
1136 int enable_bit; in fdt_get_pmu_hw_inf() local
1154 if (of_property_read_u32(np, "enable-bit-index", &enable_bit)) in fdt_get_pmu_hw_inf()
1155 enable_bit = 0; in fdt_get_pmu_hw_inf()
1157 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit); in fdt_get_pmu_hw_inf()
1165 inf->enable_mask = 1 << enable_bit; in fdt_get_pmu_hw_inf()
/drivers/tty/serial/
Dmsm_serial.c177 u32 enable_bit; member
272 val &= ~dma->enable_bit; in msm_stop_dma()
332 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE; in msm_request_tx_dma()
334 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE; in msm_request_tx_dma()
379 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE; in msm_request_rx_dma()
381 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE; in msm_request_rx_dma()
453 val &= ~dma->enable_bit; in msm_complete_tx_dma()
523 val |= dma->enable_bit; in msm_handle_tx_dma()
557 val &= ~dma->enable_bit; in msm_complete_rx_dma()
655 val |= dma->enable_bit; in msm_start_rx_dma()
/drivers/clk/spear/
Dclk-aux-synth.c41 .enable_bit = AUX_SYNT_ENB,
184 aux->masks->enable_bit, 0, lock); in clk_register_aux()
Dclk.h40 u32 enable_bit; member
/drivers/clk/bcm/
Dclk-kona.c271 u32 enable_bit; in __ccu_policy_engine_stop() local
280 enable_bit = enable->bit; in __ccu_policy_engine_stop()
281 ret = __ccu_wait_bit(ccu, offset, enable_bit, false); in __ccu_policy_engine_stop()
289 __ccu_write(ccu, offset, (u32)1 << enable_bit); in __ccu_policy_engine_stop()
292 ret = __ccu_wait_bit(ccu, offset, enable_bit, false); in __ccu_policy_engine_stop()
/drivers/phy/
Dphy-rockchip-typec.c261 u32 enable_bit; member
441 u32 val = en << reg->enable_bit; in property_enable()
695 if (!(val & BIT(reg->enable_bit))) { in rockchip_usb3_phy_power_on()
841 reg->enable_bit = buffer[1]; in tcphy_get_param()

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