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Searched refs:engine (Results 1 – 25 of 268) sorted by relevance

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/drivers/gpu/drm/nouveau/nvkm/engine/disp/
DKbuild1 nvkm-y += nvkm/engine/disp/base.o
2 nvkm-y += nvkm/engine/disp/nv04.o
3 nvkm-y += nvkm/engine/disp/nv50.o
4 nvkm-y += nvkm/engine/disp/g84.o
5 nvkm-y += nvkm/engine/disp/g94.o
6 nvkm-y += nvkm/engine/disp/gt200.o
7 nvkm-y += nvkm/engine/disp/gt215.o
8 nvkm-y += nvkm/engine/disp/gf119.o
9 nvkm-y += nvkm/engine/disp/gk104.o
10 nvkm-y += nvkm/engine/disp/gk110.o
[all …]
/drivers/gpu/drm/i915/
Dintel_lrc.c232 struct intel_engine_cs *engine);
234 struct intel_engine_cs *engine);
237 struct intel_engine_cs *engine,
273 logical_ring_init_platform_invariants(struct intel_engine_cs *engine) in logical_ring_init_platform_invariants() argument
275 struct drm_i915_private *dev_priv = engine->i915; in logical_ring_init_platform_invariants()
277 engine->disable_lite_restore_wa = in logical_ring_init_platform_invariants()
280 (engine->id == VCS || engine->id == VCS2); in logical_ring_init_platform_invariants()
282 engine->ctx_desc_template = GEN8_CTX_VALID; in logical_ring_init_platform_invariants()
284 engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT; in logical_ring_init_platform_invariants()
285 engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE; in logical_ring_init_platform_invariants()
[all …]
Dintel_ringbuffer.c179 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; in intel_emit_post_sync_nonzero_flush()
215 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; in gen6_render_ring_flush()
289 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; in gen7_render_ring_flush()
374 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; in gen8_render_ring_flush()
408 u64 intel_engine_get_active_head(struct intel_engine_cs *engine) in intel_engine_get_active_head() argument
410 struct drm_i915_private *dev_priv = engine->i915; in intel_engine_get_active_head()
414 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), in intel_engine_get_active_head()
415 RING_ACTHD_UDW(engine->mmio_base)); in intel_engine_get_active_head()
417 acthd = I915_READ(RING_ACTHD(engine->mmio_base)); in intel_engine_get_active_head()
424 static void ring_setup_phys_status_page(struct intel_engine_cs *engine) in ring_setup_phys_status_page() argument
[all …]
Dintel_engine_cs.c35 int (*init_legacy)(struct intel_engine_cs *engine);
36 int (*init_execlists)(struct intel_engine_cs *engine);
90 struct intel_engine_cs *engine = &dev_priv->engine[id]; in intel_engine_setup() local
92 engine->id = id; in intel_engine_setup()
93 engine->i915 = dev_priv; in intel_engine_setup()
94 engine->name = info->name; in intel_engine_setup()
95 engine->exec_id = info->exec_id; in intel_engine_setup()
96 engine->hw_id = engine->guc_id = info->hw_id; in intel_engine_setup()
97 engine->mmio_base = info->mmio_base; in intel_engine_setup()
98 engine->irq_shift = info->irq_shift; in intel_engine_setup()
[all …]
Dintel_ringbuffer.h35 #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base)) argument
36 #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val) argument
38 #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base)) argument
39 #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val) argument
41 #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base)) argument
42 #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val) argument
44 #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base)) argument
45 #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val) argument
47 #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base)) argument
48 #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val) argument
[all …]
Dintel_breadcrumbs.c31 struct intel_engine_cs *engine = (struct intel_engine_cs *)data; in intel_breadcrumbs_hangcheck() local
32 struct intel_breadcrumbs *b = &engine->breadcrumbs; in intel_breadcrumbs_hangcheck()
42 DRM_DEBUG("Hangcheck timer elapsed... %s idle\n", engine->name); in intel_breadcrumbs_hangcheck()
43 set_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings); in intel_breadcrumbs_hangcheck()
44 mod_timer(&engine->breadcrumbs.fake_irq, jiffies + 1); in intel_breadcrumbs_hangcheck()
55 i915_queue_hangcheck(engine->i915); in intel_breadcrumbs_hangcheck()
65 struct intel_engine_cs *engine = (struct intel_engine_cs *)data; in intel_breadcrumbs_fake_irq() local
74 if (intel_engine_wakeup(engine)) in intel_breadcrumbs_fake_irq()
75 mod_timer(&engine->breadcrumbs.fake_irq, jiffies + 1); in intel_breadcrumbs_fake_irq()
78 static void irq_enable(struct intel_engine_cs *engine) in irq_enable() argument
[all …]
Dintel_lrc.h32 #define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230) argument
33 #define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234) argument
34 #define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4) argument
35 #define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244) argument
39 #define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370) argument
40 #define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8) argument
41 #define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4) argument
42 #define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0) argument
68 void intel_logical_ring_stop(struct intel_engine_cs *engine);
69 void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
[all …]
Di915_gem_context.c149 struct intel_context *ce = &ctx->engine[i]; in i915_gem_context_free()
302 ctx->engine[RCS].state = vma; in __create_hw_context()
409 struct intel_engine_cs *engine) in i915_gem_context_unpin() argument
412 intel_lr_context_unpin(ctx, engine); in i915_gem_context_unpin()
414 struct intel_context *ce = &ctx->engine[engine->id]; in i915_gem_context_unpin()
476 struct intel_engine_cs *engine; in i915_gem_context_lost() local
480 for_each_engine(engine, dev_priv) { in i915_gem_context_lost()
481 if (engine->last_context) { in i915_gem_context_lost()
482 i915_gem_context_unpin(engine->last_context, engine); in i915_gem_context_lost()
483 engine->last_context = NULL; in i915_gem_context_lost()
[all …]
Di915_gem_request.c97 intel_engine_get_seqno(to_request(fence)->engine)); in i915_fence_timeline_value_str()
213 request->engine); in i915_gem_request_retire()
222 struct intel_engine_cs *engine = req->engine; in i915_gem_request_retire_upto() local
229 tmp = list_first_entry(&engine->request_list, in i915_gem_request_retire_upto()
258 struct intel_engine_cs *engine; in i915_gem_init_seqno() local
262 for_each_engine(engine, dev_priv) { in i915_gem_init_seqno()
263 ret = intel_engine_idle(engine, in i915_gem_init_seqno()
279 for_each_engine(engine, dev_priv) in i915_gem_init_seqno()
280 intel_engine_init_seqno(engine, seqno); in i915_gem_init_seqno()
331 request->engine->last_submitted_seqno = request->fence.seqno; in submit_notify()
[all …]
Di915_gpu_error.c33 static const char *engine_str(int engine) in engine_str() argument
35 switch (engine) { in engine_str()
199 err_puts(m, err->engine != -1 ? " " : ""); in print_error_buffers()
200 err_puts(m, engine_str(err->engine)); in print_error_buffers()
356 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { in i915_error_state_to_str()
357 if (error->engine[i].hangcheck_score > max_hangcheck_score) in i915_error_state_to_str()
358 max_hangcheck_score = error->engine[i].hangcheck_score; in i915_error_state_to_str()
360 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { in i915_error_state_to_str()
361 if (error->engine[i].hangcheck_score == max_hangcheck_score && in i915_error_state_to_str()
362 error->engine[i].pid != -1) { in i915_error_state_to_str()
[all …]
Di915_cmd_parser.c615 static bool validate_cmds_sorted(const struct intel_engine_cs *engine, in validate_cmds_sorted() argument
638 engine->name, engine->id, in validate_cmds_sorted()
650 static bool check_sorted(const struct intel_engine_cs *engine, in check_sorted() argument
664 engine->name, engine->id, in check_sorted()
675 static bool validate_regs_sorted(struct intel_engine_cs *engine) in validate_regs_sorted() argument
680 for (i = 0; i < engine->reg_table_count; i++) { in validate_regs_sorted()
681 table = &engine->reg_tables[i]; in validate_regs_sorted()
682 if (!check_sorted(engine, table->regs, table->num_regs)) in validate_regs_sorted()
724 static int init_hash_table(struct intel_engine_cs *engine, in init_hash_table() argument
730 hash_init(engine->cmd_hash); in init_hash_table()
[all …]
/drivers/gpu/drm/nouveau/nvkm/core/
Dengine.c33 struct nvkm_engine *engine = *pengine; in nvkm_engine_unref() local
34 if (engine) { in nvkm_engine_unref()
35 mutex_lock(&engine->subdev.mutex); in nvkm_engine_unref()
36 if (--engine->usecount == 0) in nvkm_engine_unref()
37 nvkm_subdev_fini(&engine->subdev, false); in nvkm_engine_unref()
38 mutex_unlock(&engine->subdev.mutex); in nvkm_engine_unref()
44 nvkm_engine_ref(struct nvkm_engine *engine) in nvkm_engine_ref() argument
46 if (engine) { in nvkm_engine_ref()
47 mutex_lock(&engine->subdev.mutex); in nvkm_engine_ref()
48 if (++engine->usecount == 1) { in nvkm_engine_ref()
[all …]
/drivers/gpu/drm/nouveau/nvkm/engine/gr/
DKbuild1 nvkm-y += nvkm/engine/gr/base.o
2 nvkm-y += nvkm/engine/gr/nv04.o
3 nvkm-y += nvkm/engine/gr/nv10.o
4 nvkm-y += nvkm/engine/gr/nv15.o
5 nvkm-y += nvkm/engine/gr/nv17.o
6 nvkm-y += nvkm/engine/gr/nv20.o
7 nvkm-y += nvkm/engine/gr/nv25.o
8 nvkm-y += nvkm/engine/gr/nv2a.o
9 nvkm-y += nvkm/engine/gr/nv30.o
10 nvkm-y += nvkm/engine/gr/nv34.o
[all …]
Dbase.c29 nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile) in nvkm_gr_tile() argument
31 struct nvkm_gr *gr = nvkm_gr(engine); in nvkm_gr_tile()
55 struct nvkm_gr *gr = nvkm_gr(oclass->engine); in nvkm_gr_oclass_get()
80 struct nvkm_gr *gr = nvkm_gr(oclass->engine); in nvkm_gr_cclass_new()
87 nvkm_gr_intr(struct nvkm_engine *engine) in nvkm_gr_intr() argument
89 struct nvkm_gr *gr = nvkm_gr(engine); in nvkm_gr_intr()
94 nvkm_gr_oneinit(struct nvkm_engine *engine) in nvkm_gr_oneinit() argument
96 struct nvkm_gr *gr = nvkm_gr(engine); in nvkm_gr_oneinit()
103 nvkm_gr_init(struct nvkm_engine *engine) in nvkm_gr_init() argument
105 struct nvkm_gr *gr = nvkm_gr(engine); in nvkm_gr_init()
[all …]
/drivers/video/fbdev/via/
Daccel.c27 static int viafb_set_bpp(void __iomem *engine, u8 bpp) in viafb_set_bpp() argument
33 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc; in viafb_set_bpp()
48 writel(gemode, engine + VIA_REG_GEMODE); in viafb_set_bpp()
53 static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height, in hw_bitblt_1() argument
93 ret = viafb_set_bpp(engine, dst_bpp); in hw_bitblt_1()
105 writel(tmp, engine + 0x08); in hw_bitblt_1()
114 writel(tmp, engine + 0x0C); in hw_bitblt_1()
122 writel(tmp, engine + 0x10); in hw_bitblt_1()
125 writel(fg_color, engine + 0x18); in hw_bitblt_1()
128 writel(bg_color, engine + 0x1C); in hw_bitblt_1()
[all …]
/drivers/crypto/
Dpicoxcell_crypto.c94 struct spacc_engine *engine; member
108 struct spacc_engine *engine; member
151 struct spacc_engine *engine; member
159 struct spacc_engine *engine; member
199 static inline int spacc_fifo_cmd_full(struct spacc_engine *engine) in spacc_fifo_cmd_full() argument
201 u32 fifo_stat = readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET); in spacc_fifo_cmd_full()
217 return is_cipher_ctx ? ctx->engine->cipher_ctx_base + in spacc_ctx_page_addr()
218 (indx * ctx->engine->cipher_pg_sz) : in spacc_ctx_page_addr()
219 ctx->engine->hash_key_base + (indx * ctx->engine->hash_pg_sz); in spacc_ctx_page_addr()
253 unsigned indx = ctx->engine->next_ctx++; in spacc_load_ctx()
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/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
DKbuild1 nvkm-y += nvkm/engine/fifo/base.o
2 nvkm-y += nvkm/engine/fifo/nv04.o
3 nvkm-y += nvkm/engine/fifo/nv10.o
4 nvkm-y += nvkm/engine/fifo/nv17.o
5 nvkm-y += nvkm/engine/fifo/nv40.o
6 nvkm-y += nvkm/engine/fifo/nv50.o
7 nvkm-y += nvkm/engine/fifo/g84.o
8 nvkm-y += nvkm/engine/fifo/gf100.o
9 nvkm-y += nvkm/engine/fifo/gk104.o
10 nvkm-y += nvkm/engine/fifo/gk110.o
[all …]
Dchan.c43 struct nvkm_engine *engine = object->oproxy.object->engine; in nvkm_fifo_chan_child_fini() local
45 struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; in nvkm_fifo_chan_child_fini()
46 const char *name = nvkm_subdev_name[engine->subdev.index]; in nvkm_fifo_chan_child_fini()
53 ret = chan->func->engine_fini(chan, engine, suspend); in nvkm_fifo_chan_child_fini()
76 struct nvkm_engine *engine = object->oproxy.object->engine; in nvkm_fifo_chan_child_init() local
78 struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; in nvkm_fifo_chan_child_init()
79 const char *name = nvkm_subdev_name[engine->subdev.index]; in nvkm_fifo_chan_child_init()
92 ret = chan->func->engine_init(chan, engine); in nvkm_fifo_chan_child_init()
109 struct nvkm_engine *engine = object->oproxy.base.engine; in nvkm_fifo_chan_child_del() local
111 struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; in nvkm_fifo_chan_child_del()
[all …]
Dgk104.c53 struct nvkm_device *device = fifo->engine.subdev.device; in gk104_fifo_uevent_fini()
60 struct nvkm_device *device = fifo->engine.subdev.device; in gk104_fifo_uevent_init()
68 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; in gk104_fifo_runlist_commit()
106 mutex_lock(&fifo->base.engine.subdev.mutex); in gk104_fifo_runlist_remove()
108 mutex_unlock(&fifo->base.engine.subdev.mutex); in gk104_fifo_runlist_remove()
114 mutex_lock(&fifo->base.engine.subdev.mutex); in gk104_fifo_runlist_insert()
116 mutex_unlock(&fifo->base.engine.subdev.mutex); in gk104_fifo_runlist_insert()
123 struct nvkm_device *device = fifo->base.engine.subdev.device; in gk104_fifo_recover_work()
124 struct nvkm_engine *engine; in gk104_fifo_recover_work() local
139 if ((engine = fifo->engine[engn].engine)) { in gk104_fifo_recover_work()
[all …]
/drivers/crypto/marvell/
Dcesa.c44 mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine, in mv_cesa_dequeue_req_locked() argument
49 *backlog = crypto_get_backlog(&engine->queue); in mv_cesa_dequeue_req_locked()
50 req = crypto_dequeue_request(&engine->queue); in mv_cesa_dequeue_req_locked()
58 static void mv_cesa_rearm_engine(struct mv_cesa_engine *engine) in mv_cesa_rearm_engine() argument
64 spin_lock_bh(&engine->lock); in mv_cesa_rearm_engine()
65 if (!engine->req) { in mv_cesa_rearm_engine()
66 req = mv_cesa_dequeue_req_locked(engine, &backlog); in mv_cesa_rearm_engine()
67 engine->req = req; in mv_cesa_rearm_engine()
69 spin_unlock_bh(&engine->lock); in mv_cesa_rearm_engine()
83 static int mv_cesa_std_process(struct mv_cesa_engine *engine, u32 status) in mv_cesa_std_process() argument
[all …]
Dtdma.c42 struct mv_cesa_engine *engine = dreq->engine; in mv_cesa_dma_step() local
44 writel_relaxed(0, engine->regs + CESA_SA_CFG); in mv_cesa_dma_step()
46 mv_cesa_set_int_mask(engine, CESA_SA_INT_ACC0_IDMA_DONE); in mv_cesa_dma_step()
49 engine->regs + CESA_TDMA_CONTROL); in mv_cesa_dma_step()
53 engine->regs + CESA_SA_CFG); in mv_cesa_dma_step()
55 engine->regs + CESA_TDMA_NEXT_ADDR); in mv_cesa_dma_step()
56 BUG_ON(readl(engine->regs + CESA_SA_CMD) & in mv_cesa_dma_step()
58 writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD); in mv_cesa_dma_step()
86 struct mv_cesa_engine *engine) in mv_cesa_dma_prepare() argument
92 tdma->dst = cpu_to_le32(tdma->dst + engine->sram_dma); in mv_cesa_dma_prepare()
[all …]
/drivers/gpu/drm/nouveau/nvkm/engine/
DKbuild1 nvkm-y += nvkm/engine/falcon.o
2 nvkm-y += nvkm/engine/xtensa.o
4 include $(src)/nvkm/engine/bsp/Kbuild
5 include $(src)/nvkm/engine/ce/Kbuild
6 include $(src)/nvkm/engine/cipher/Kbuild
7 include $(src)/nvkm/engine/device/Kbuild
8 include $(src)/nvkm/engine/disp/Kbuild
9 include $(src)/nvkm/engine/dma/Kbuild
10 include $(src)/nvkm/engine/fifo/Kbuild
11 include $(src)/nvkm/engine/gr/Kbuild
[all …]
/drivers/gpu/drm/via/
Dvia_dmablit.c209 via_fire_dmablit(struct drm_device *dev, drm_via_sg_info_t *vsg, int engine) in via_fire_dmablit() argument
213 VIA_WRITE(VIA_PCI_DMA_MAR0 + engine*0x10, 0); in via_fire_dmablit()
214 VIA_WRITE(VIA_PCI_DMA_DAR0 + engine*0x10, 0); in via_fire_dmablit()
215 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD | in via_fire_dmablit()
217 VIA_WRITE(VIA_PCI_DMA_MR0 + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE); in via_fire_dmablit()
218 VIA_WRITE(VIA_PCI_DMA_BCR0 + engine*0x10, 0); in via_fire_dmablit()
219 VIA_WRITE(VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start); in via_fire_dmablit()
221 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS); in via_fire_dmablit()
222 VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04); in via_fire_dmablit()
289 via_abort_dmablit(struct drm_device *dev, int engine) in via_abort_dmablit() argument
[all …]
/drivers/gpu/drm/nouveau/nvkm/engine/dma/
DKbuild1 nvkm-y += nvkm/engine/dma/base.o
2 nvkm-y += nvkm/engine/dma/nv04.o
3 nvkm-y += nvkm/engine/dma/nv50.o
4 nvkm-y += nvkm/engine/dma/gf100.o
5 nvkm-y += nvkm/engine/dma/gf119.o
7 nvkm-y += nvkm/engine/dma/user.o
8 nvkm-y += nvkm/engine/dma/usernv04.o
9 nvkm-y += nvkm/engine/dma/usernv50.o
10 nvkm-y += nvkm/engine/dma/usergf100.o
11 nvkm-y += nvkm/engine/dma/usergf119.o
/drivers/gpu/drm/nouveau/nvkm/engine/pm/
DKbuild1 nvkm-y += nvkm/engine/pm/base.o
2 nvkm-y += nvkm/engine/pm/nv40.o
3 nvkm-y += nvkm/engine/pm/nv50.o
4 nvkm-y += nvkm/engine/pm/g84.o
5 nvkm-y += nvkm/engine/pm/gt200.o
6 nvkm-y += nvkm/engine/pm/gt215.o
7 nvkm-y += nvkm/engine/pm/gf100.o
8 nvkm-y += nvkm/engine/pm/gf108.o
9 nvkm-y += nvkm/engine/pm/gf117.o
10 nvkm-y += nvkm/engine/pm/gk104.o

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