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Searched refs:gpu_read (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/etnaviv/
Detnaviv_gpu.c147 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
148 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); in etnaviv_hw_specs()
149 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); in etnaviv_hw_specs()
150 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); in etnaviv_hw_specs()
294 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); in etnaviv_hw_identify()
303 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); in etnaviv_hw_identify()
304 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); in etnaviv_hw_identify()
319 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); in etnaviv_hw_identify()
320 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); in etnaviv_hw_identify()
347 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); in etnaviv_hw_identify()
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Detnaviv_gpu.h181 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() function
Detnaviv_dump.c93 reg->value = gpu_read(gpu, etnaviv_dump_registers[i]); in etnaviv_core_dump_registers()
Detnaviv_iommu_v2.c251 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore()
/drivers/gpu/drm/msm/adreno/
Da4xx_gpu.c235 val = gpu_read(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ); in a4xx_hw_init()
309 gpu_read(gpu, REG_A4XX_RBBM_SW_RESET_CMD); in a4xx_recover()
337 if (spin_until(!(gpu_read(gpu, REG_A4XX_RBBM_STATUS) & in a4xx_idle()
348 status = gpu_read(gpu, REG_A4XX_RBBM_INT_0_STATUS); in a4xx_irq()
352 uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS); in a4xx_irq()
453 gpu_read(gpu, REG_A4XX_RBBM_STATUS)); in a4xx_show()
549 gpu_read(gpu, REG_A4XX_RBBM_STATUS)); in a4xx_dump()
567 reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS); in a4xx_pm_resume()
592 tmp = gpu_read(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_HI); in a4xx_get_timestamp()
595 lo = gpu_read(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO); in a4xx_get_timestamp()
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Da3xx_gpu.c311 gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD); in a3xx_recover()
339 if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) & in a3xx_idle()
350 status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS); in a3xx_irq()
407 gpu_read(gpu, REG_A3XX_RBBM_STATUS)); in a3xx_show()
417 gpu_read(gpu, REG_A3XX_RBBM_STATUS)); in a3xx_dump()
Dadreno_gpu.c270 uint32_t val = gpu_read(gpu, addr); in adreno_show()
303 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in adreno_dump_info()
321 uint32_t val = gpu_read(gpu, addr); in adreno_dump()
Dadreno_gpu.h302 val = gpu_read(&gpu->base, reg - 1); in adreno_gpu_read()
/drivers/gpu/drm/msm/
Dmsm_gpu.h152 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) in gpu_read() function
Dmsm_gpu.c365 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); in update_hw_cntrs()