Home
last modified time | relevance | path

Searched refs:hdmi_read (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/msm/hdmi/
Dhdmi_hdcp.c212 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL); in msm_hdmi_hdcp_irq()
237 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); in msm_hdmi_hdcp_irq()
297 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS); in msm_reset_hdcp_ddc_failures()
318 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_CTRL_1); in msm_reset_hdcp_ddc_failures()
323 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS); in msm_reset_hdcp_ddc_failures()
334 hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS)); in msm_reset_hdcp_ddc_failures()
336 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); in msm_reset_hdcp_ddc_failures()
342 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); in msm_reset_hdcp_ddc_failures()
347 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); in msm_reset_hdcp_ddc_failures()
355 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); in msm_reset_hdcp_ddc_failures()
[all …]
Dhdmi_i2c.c64 ddc_int_ctrl = hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL); in ddc_clear_irq()
87 ddc_int_ctrl = hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL); in sw_done()
116 WARN_ON(!(hdmi_read(hdmi, REG_HDMI_CTRL) & HDMI_CTRL_ENABLE)); in msm_hdmi_i2c_xfer()
180 hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS), in msm_hdmi_i2c_xfer()
181 hdmi_read(hdmi, REG_HDMI_DDC_HW_STATUS), in msm_hdmi_i2c_xfer()
182 hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL)); in msm_hdmi_i2c_xfer()
186 ddc_status = hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS); in msm_hdmi_i2c_xfer()
208 hdmi_read(hdmi, REG_HDMI_DDC_DATA); in msm_hdmi_i2c_xfer()
211 ddc_data = hdmi_read(hdmi, REG_HDMI_DDC_DATA); in msm_hdmi_i2c_xfer()
Dhdmi_audio.c122 acr_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_ACR_PKT_CTRL); in msm_hdmi_audio_update()
123 vbi_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_VBI_PKT_CTRL); in msm_hdmi_audio_update()
124 aud_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_AUDIO_PKT_CTRL1); in msm_hdmi_audio_update()
125 infofrm_ctrl = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL0); in msm_hdmi_audio_update()
126 audio_config = hdmi_read(hdmi, REG_HDMI_AUDIO_CFG); in msm_hdmi_audio_update()
Dhdmi_connector.c35 val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL); in msm_hdmi_phy_reset()
200 hpd_ctrl = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); in hpd_enable()
263 hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); in msm_hdmi_connector_irq()
264 hpd_int_ctrl = hdmi_read(hdmi, REG_HDMI_HPD_INT_CTRL); in msm_hdmi_connector_irq()
288 uint32_t hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); in detect_reg()
362 hdmi_ctrl = hdmi_read(hdmi, REG_HDMI_CTRL); in msm_hdmi_connector_get_modes()
Dhdmi.h133 static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg) in hdmi_read() function
/drivers/media/i2c/
Dadv7842.c537 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) in hdmi_read() function
553 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); in hdmi_write_and_or()
911 reg->val = hdmi_read(sd, reg->reg & 0xff); in adv7842_g_register()
1186 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; in set_rgb_quantization_range()
1384 return hdmi_read(sd, 0x05) & 0x80; in is_hdmi()
1574 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); in adv7842_query_dv_timings()
1575 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); in adv7842_query_dv_timings()
1576 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000; in adv7842_query_dv_timings()
1577 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813); in adv7842_query_dv_timings()
1580 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8); in adv7842_query_dv_timings()
[all …]
Dadv7604.c540 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) in hdmi_read() function
549 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; in hdmi_read16()
561 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); in hdmi_write_clr_set()
1104 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; in set_rgb_quantization_range()
1286 return hdmi_read(sd, 0x05) & 0x80; in is_hdmi()
1445 polarity = hdmi_read(sd, 0x05); in read_stdi()
1514 a = hdmi_read(sd, 0x06); in adv7604_read_hdmi_pixelclock()
1515 b = hdmi_read(sd, 0x3b); in adv7604_read_hdmi_pixelclock()
1522 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; in adv7604_read_hdmi_pixelclock()
1534 a = hdmi_read(sd, 0x51); in adv7611_read_hdmi_pixelclock()
[all …]
/drivers/gpu/drm/sti/
Dsti_hdmi.c168 u32 hdmi_read(struct sti_hdmi *hdmi, int offset) in hdmi_read() function
221 hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA); in hdmi_irq()
227 hdmi_read(hdmi, HDMI_INT_STA); in hdmi_irq()
324 val = hdmi_read(hdmi, HDMI_SW_DI_CFG); in hdmi_infoframe_reset()
392 val = hdmi_read(hdmi, HDMI_SW_DI_CFG); in hdmi_infoframe_write_infopack()
417 val = hdmi_read(hdmi, HDMI_SW_DI_CFG); in hdmi_infoframe_write_infopack()
494 val = hdmi_read(hdmi, HDMI_SW_DI_CFG); in hdmi_audio_infoframe_config()
565 val = hdmi_read(hdmi, HDMI_CFG); in hdmi_swreset()
579 if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0) in hdmi_swreset()
582 val = hdmi_read(hdmi, HDMI_CFG); in hdmi_swreset()
[all …]
Dsti_hdmi_tx3g4c28phy.c124 if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK) == 0) { in sti_hdmi_tx3g4c28phy_start()
204 if (hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK) in sti_hdmi_tx3g4c28phy_stop()
Dsti_hdmi.h107 u32 hdmi_read(struct sti_hdmi *hdmi, int offset);