Home
last modified time | relevance | path

Searched refs:hscx (Results 1 – 25 of 28) sorted by relevance

12

/drivers/isdn/hisax/
Dhscx_irq.c17 waitforCEC(struct IsdnCardState *cs, int hscx) in waitforCEC() argument
21 while ((READHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) { in waitforCEC()
31 waitforXFW(struct IsdnCardState *cs, int hscx) in waitforXFW() argument
35 while (((READHSCX(cs, hscx, HSCX_STAR) & 0x44) != 0x40) && to) { in waitforXFW()
44 WriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u_char data) in WriteHSCXCMDR() argument
46 waitforCEC(cs, hscx); in WriteHSCXCMDR()
47 WRITEHSCX(cs, hscx, HSCX_CMDR, data); in WriteHSCXCMDR()
61 if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) { in hscx_empty_fifo()
64 WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80); in hscx_empty_fifo()
65 bcs->hw.hscx.rcvidx = 0; in hscx_empty_fifo()
[all …]
Dhscx.c44 int hscx = bcs->hw.hscx.hscx; in modehscx() local
48 'A' + hscx, mode, bc); in modehscx()
51 cs->BC_Write_Reg(cs, hscx, HSCX_XAD1, 0xFF); in modehscx()
52 cs->BC_Write_Reg(cs, hscx, HSCX_XAD2, 0xFF); in modehscx()
53 cs->BC_Write_Reg(cs, hscx, HSCX_RAH2, 0xFF); in modehscx()
54 cs->BC_Write_Reg(cs, hscx, HSCX_XBCH, 0x0); in modehscx()
55 cs->BC_Write_Reg(cs, hscx, HSCX_RLCR, 0x0); in modehscx()
56 cs->BC_Write_Reg(cs, hscx, HSCX_CCR1, in modehscx()
58 cs->BC_Write_Reg(cs, hscx, HSCX_CCR2, 0x30); in modehscx()
59 cs->BC_Write_Reg(cs, hscx, HSCX_XCCR, 7); in modehscx()
[all …]
Djade_irq.c51 if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) { in jade_empty_fifo()
54 WriteJADECMDR(cs, bcs->hw.hscx.hscx, jade_HDLC_RCMD, jadeRCMD_RMC); in jade_empty_fifo()
55 bcs->hw.hscx.rcvidx = 0; in jade_empty_fifo()
58 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx; in jade_empty_fifo()
59 bcs->hw.hscx.rcvidx += count; in jade_empty_fifo()
60 READJADEFIFO(cs, bcs->hw.hscx.hscx, ptr, count); in jade_empty_fifo()
61 WriteJADECMDR(cs, bcs->hw.hscx.hscx, jade_HDLC_RCMD, jadeRCMD_RMC); in jade_empty_fifo()
66 bcs->hw.hscx.hscx ? 'B' : 'A', count); in jade_empty_fifo()
95 waitforXFW(cs, bcs->hw.hscx.hscx); in jade_fill_fifo()
99 bcs->hw.hscx.count += count; in jade_fill_fifo()
[all …]
Dipacx.c47 static void bch_int(struct IsdnCardState *cs, u_char hscx);
52 static void bch_init(struct IsdnCardState *cs, int hscx);
460 bcs->hw.hscx.count = 0; in bch_l2l1()
472 bcs->hw.hscx.count = 0; in bch_l2l1()
511 u_char *ptr, hscx; in bch_empty_fifo() local
516 hscx = bcs->hw.hscx.hscx; in bch_empty_fifo()
521 if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) { in bch_empty_fifo()
524 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC in bch_empty_fifo()
525 bcs->hw.hscx.rcvidx = 0; in bch_empty_fifo()
529 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx; in bch_empty_fifo()
[all …]
Dteles3.c80 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
82 return (readreg(cs->hw.teles3.hscx[hscx], offset)); in ReadHSCX()
86 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
88 writereg(cs->hw.teles3.hscx[hscx], offset, value); in WriteHSCX()
95 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.hscx[nr], reg)
96 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.hscx[nr], reg, data)
112 val = readreg(cs->hw.teles3.hscx[1], HSCX_ISTA); in teles3_interrupt()
121 val = readreg(cs->hw.teles3.hscx[1], HSCX_ISTA); in teles3_interrupt()
135 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); in teles3_interrupt()
136 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); in teles3_interrupt()
[all …]
DMakefile30 hisax-$(CONFIG_HISAX_16_0) += teles0.o isac.o arcofi.o hscx.o
31 hisax-$(CONFIG_HISAX_16_3) += teles3.o isac.o arcofi.o hscx.o
32 hisax-$(CONFIG_HISAX_TELESPCI) += telespci.o isac.o arcofi.o hscx.o
33 hisax-$(CONFIG_HISAX_S0BOX) += s0box.o isac.o arcofi.o hscx.o
34 hisax-$(CONFIG_HISAX_AVM_A1) += avm_a1.o isac.o arcofi.o hscx.o
35 hisax-$(CONFIG_HISAX_AVM_A1_PCMCIA) += avm_a1p.o isac.o arcofi.o hscx.o
37 hisax-$(CONFIG_HISAX_ELSA) += elsa.o isac.o arcofi.o hscx.o
38 hisax-$(CONFIG_HISAX_IX1MICROR2) += ix1_micro.o isac.o arcofi.o hscx.o
39 hisax-$(CONFIG_HISAX_DIEHLDIVA) += diva.o isac.o arcofi.o hscx.o ipacx.o
40 hisax-$(CONFIG_HISAX_ASUSCOM) += asuscom.o isac.o arcofi.o hscx.o
[all …]
Ddiva.c180 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
183 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
187 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
190 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0), value); in WriteHSCX()
220 MemReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in MemReadHSCX() argument
222 return (memreadreg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0))); in MemReadHSCX()
226 MemWriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in MemWriteHSCX() argument
228 memwritereg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0), value); in MemWriteHSCX()
259 MemReadHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset) in MemReadHSCX_IPACX() argument
262 (hscx ? IPACX_OFF_B2 : IPACX_OFF_B1))); in MemReadHSCX_IPACX()
[all …]
Davm_a1.c80 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
82 return (readreg(cs->hw.avm.hscx[hscx], offset)); in ReadHSCX()
86 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
88 writereg(cs->hw.avm.hscx[hscx], offset, value); in WriteHSCX()
95 #define READHSCX(cs, nr, reg) readreg(cs->hw.avm.hscx[nr], reg)
96 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.avm.hscx[nr], reg, data)
117 val = readreg(cs->hw.avm.hscx[1], HSCX_ISTA); in avm_a1_interrupt()
127 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0xFF); in avm_a1_interrupt()
128 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0xFF); in avm_a1_interrupt()
131 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0x0); in avm_a1_interrupt()
[all …]
Dgazel.c169 ReadHSCXfifo(struct IsdnCardState *cs, int hscx, u_char *data, int size) in ReadHSCXfifo() argument
174 read_fifo(cs->hw.gazel.hscxfifo[hscx], data, size); in ReadHSCXfifo()
178 read_fifo_ipac(cs->hw.gazel.ipac, hscx * 0x40, data, size); in ReadHSCXfifo()
184 WriteHSCXfifo(struct IsdnCardState *cs, int hscx, u_char *data, int size) in WriteHSCXfifo() argument
189 write_fifo(cs->hw.gazel.hscxfifo[hscx], data, size); in WriteHSCXfifo()
193 write_fifo_ipac(cs->hw.gazel.ipac, hscx * 0x40, data, size); in WriteHSCXfifo()
199 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
207 return (readreg(cs->hw.gazel.hscx[hscx], off2)); in ReadHSCX()
210 return (readreg_ipac(cs->hw.gazel.ipac, hscx * 0x40 + off2)); in ReadHSCX()
216 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
[all …]
Ds0box.c120 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
122 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset)); in ReadHSCX()
126 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
128 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value); in WriteHSCX()
135 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg)
136 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, d…
152 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_ISTA); in s0box_interrupt()
161 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_ISTA); in s0box_interrupt()
175 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); in s0box_interrupt()
176 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); in s0box_interrupt()
[all …]
Dmic.c90 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
93 cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
97 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
100 cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0), value); in WriteHSCX()
108 cs->hw.mic.hscx, reg + (nr ? 0x40 : 0))
110 cs->hw.mic.hscx, reg + (nr ? 0x40 : 0), data)
113 cs->hw.mic.hscx, (nr ? 0x40 : 0), ptr, cnt)
116 cs->hw.mic.hscx, (nr ? 0x40 : 0), ptr, cnt)
128 val = readreg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_ISTA + 0x40); in mic_interrupt()
136 val = readreg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_ISTA + 0x40); in mic_interrupt()
[all …]
Dsaphir.c92 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
94 return (readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, in ReadHSCX()
95 offset + (hscx ? 0x40 : 0))); in ReadHSCX()
99 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
101 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, in WriteHSCX()
102 offset + (hscx ? 0x40 : 0), value); in WriteHSCX()
106 cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0))
108 cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0), data)
111 cs->hw.saphir.hscx, (nr ? 0x40 : 0), ptr, cnt)
114 cs->hw.saphir.hscx, (nr ? 0x40 : 0), ptr, cnt)
[all …]
Dix1_micro.c100 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
103 cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
107 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
110 cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0), value); in WriteHSCX()
114 cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0))
116 cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0), data)
119 cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt)
122 cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt)
134 val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); in ix1micro_interrupt()
142 val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); in ix1micro_interrupt()
[all …]
Dniccy.c98 static u_char ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
101 cs->hw.niccy.hscx, offset + (hscx ? 0x40 : 0)); in ReadHSCX()
104 static void WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, in WriteHSCX() argument
108 cs->hw.niccy.hscx, offset + (hscx ? 0x40 : 0), value); in WriteHSCX()
112 cs->hw.niccy.hscx, reg + (nr ? 0x40 : 0))
114 cs->hw.niccy.hscx, reg + (nr ? 0x40 : 0), data)
117 cs->hw.niccy.hscx, (nr ? 0x40 : 0), ptr, cnt)
120 cs->hw.niccy.hscx, (nr ? 0x40 : 0), ptr, cnt)
140 val = readreg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, in niccy_interrupt()
149 val = readreg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, in niccy_interrupt()
[all …]
Djade.c81 int jade = bcs->hw.hscx.hscx; in modejade()
145 bcs->hw.hscx.count = 0; in jade_l2l1()
157 bcs->hw.hscx.count = 0; in jade_l2l1()
195 kfree(bcs->hw.hscx.rcvbuf); in close_jadestate()
196 bcs->hw.hscx.rcvbuf = NULL; in close_jadestate()
213 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) { in open_jadestate()
223 kfree(bcs->hw.hscx.rcvbuf); in open_jadestate()
224 bcs->hw.hscx.rcvbuf = NULL; in open_jadestate()
233 bcs->hw.hscx.rcvidx = 0; in open_jadestate()
281 cs->bcs[0].hw.hscx.hscx = 0; in initjade()
[all …]
Dsedlbauer.c202 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
205 cs->hw.sedl.hscx, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
209 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
212 cs->hw.sedl.hscx, offset + (hscx ? 0x40 : 0), value); in WriteHSCX()
225 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, offset)); in ReadISAR()
228 return (bytein(cs->hw.sedl.hscx)); in ReadISAR()
235 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, offset, value); in WriteISAR()
239 byteout(cs->hw.sedl.hscx, value); in WriteISAR()
248 cs->hw.sedl.hscx, reg + (nr ? 0x40 : 0))
250 cs->hw.sedl.hscx, reg + (nr ? 0x40 : 0), data)
[all …]
Dsportster.c78 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
80 return (bytein(calc_off(cs->hw.spt.hscx[hscx], offset))); in ReadHSCX()
84 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
86 byteout(calc_off(cs->hw.spt.hscx[hscx], offset), value); in WriteHSCX()
93 #define READHSCX(cs, nr, reg) bytein(calc_off(cs->hw.spt.hscx[nr], reg))
94 #define WRITEHSCX(cs, nr, reg, data) byteout(calc_off(cs->hw.spt.hscx[nr], reg), data)
95 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.spt.hscx[nr], ptr, cnt)
96 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.spt.hscx[nr], ptr, cnt)
225 cs->hw.spt.hscx[0] = cs->hw.spt.cfg_reg + SPORTSTER_HSCXA; in setup_sportster()
226 cs->hw.spt.hscx[1] = cs->hw.spt.cfg_reg + SPORTSTER_HSCXB; in setup_sportster()
Dasuscom.c126 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
129 cs->hw.asus.hscx, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
133 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
136 cs->hw.asus.hscx, offset + (hscx ? 0x40 : 0), value); in WriteHSCX()
144 cs->hw.asus.hscx, reg + (nr ? 0x40 : 0))
146 cs->hw.asus.hscx, reg + (nr ? 0x40 : 0), data)
149 cs->hw.asus.hscx, (nr ? 0x40 : 0), ptr, cnt)
152 cs->hw.asus.hscx, (nr ? 0x40 : 0), ptr, cnt)
164 val = readreg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_ISTA + 0x40); in asuscom_interrupt()
172 val = readreg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_ISTA + 0x40); in asuscom_interrupt()
[all …]
Dtelespci.c77 readhscx(void __iomem *adr, int hscx, u_char off) in readhscx() argument
83 writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200); in readhscx()
93 writehscx(void __iomem *adr, int hscx, u_char off, u_char data) in writehscx() argument
99 writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200); in writehscx()
143 read_fifo_hscx(void __iomem *adr, int hscx, u_char *data, int size) in read_fifo_hscx() argument
152 writel(WRITE_ADDR_HSCX | (hscx ? 0x5F : 0x1F), adr + 0x200); in read_fifo_hscx()
161 write_fifo_hscx(void __iomem *adr, int hscx, u_char *data, int size) in write_fifo_hscx() argument
170 writel(WRITE_ADDR_HSCX | (hscx ? 0x5F : 0x1F), adr + 0x200); in write_fifo_hscx()
205 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
207 return (readhscx(cs->hw.teles0.membase, hscx, offset)); in ReadHSCX()
[all …]
Dteles0.c44 readhscx(void __iomem *adr, int hscx, u_char off) in readhscx() argument
46 return readb(adr + (hscx ? 0x1c0 : 0x180) + in readhscx()
51 writehscx(void __iomem *adr, int hscx, u_char off, u_char data) in writehscx() argument
53 writeb(data, adr + (hscx ? 0x1c0 : 0x180) + in writehscx()
77 read_fifo_hscx(void __iomem *adr, int hscx, u_char *data, int size) in read_fifo_hscx() argument
80 register u_char __iomem *ad = adr + (hscx ? 0x1c0 : 0x180); in read_fifo_hscx()
86 write_fifo_hscx(void __iomem *adr, int hscx, u_char *data, int size) in write_fifo_hscx() argument
89 register u_char __iomem *ad = adr + (hscx ? 0x1c0 : 0x180); in write_fifo_hscx()
122 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
124 return (readhscx(cs->hw.teles0.membase, hscx, offset)); in ReadHSCX()
[all …]
Davm_a1p.c95 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
101 HSCX_REG_OFFSET + hscx * HSCX_CH_DIFF + offset); in ReadHSCX()
107 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
111 HSCX_REG_OFFSET + hscx * HSCX_CH_DIFF + offset); in WriteHSCX()
116 ReadHSCXfifo(struct IsdnCardState *cs, int hscx, u_char *data, int size) in ReadHSCXfifo() argument
119 HSCX_FIFO_OFFSET + hscx * HSCX_CH_DIFF); in ReadHSCXfifo()
124 WriteHSCXfifo(struct IsdnCardState *cs, int hscx, u_char *data, int size) in WriteHSCXfifo() argument
127 HSCX_FIFO_OFFSET + hscx * HSCX_CH_DIFF); in WriteHSCXfifo()
Delsa.c224 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
227 cs->hw.elsa.hscx, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
231 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
234 cs->hw.elsa.hscx, offset + (hscx ? 0x40 : 0), value); in WriteHSCX()
271 cs->hw.elsa.hscx, reg + (nr ? 0x40 : 0))
273 cs->hw.elsa.hscx, reg + (nr ? 0x40 : 0), data)
276 cs->hw.elsa.hscx, (nr ? 0x40 : 0), ptr, cnt)
279 cs->hw.elsa.hscx, (nr ? 0x40 : 0), ptr, cnt)
307 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40); in elsa_interrupt()
317 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40); in elsa_interrupt()
[all …]
Dhisax.h365 int hscx; member
523 struct hscx_hw hscx; member
560 unsigned int hscx; member
584 signed int hscx[2]; member
598 unsigned int hscx[2]; member
610 unsigned int hscx; member
620 unsigned int hscx; member
631 unsigned int hscx; member
651 unsigned int hscx; member
663 unsigned int hscx[2]; member
[all …]
/drivers/isdn/hardware/mISDN/
DmISDNipac.c941 hscx_empty_fifo(struct hscx_hw *hscx, u8 count) in hscx_empty_fifo() argument
946 pr_debug("%s: B%1d %d\n", hscx->ip->name, hscx->bch.nr, count); in hscx_empty_fifo()
947 if (test_bit(FLG_RX_OFF, &hscx->bch.Flags)) { in hscx_empty_fifo()
948 hscx->bch.dropcnt += count; in hscx_empty_fifo()
949 hscx_cmdr(hscx, 0x80); /* RMC */ in hscx_empty_fifo()
952 maxlen = bchannel_get_rxbuf(&hscx->bch, count); in hscx_empty_fifo()
954 hscx_cmdr(hscx, 0x80); /* RMC */ in hscx_empty_fifo()
955 if (hscx->bch.rx_skb) in hscx_empty_fifo()
956 skb_trim(hscx->bch.rx_skb, 0); in hscx_empty_fifo()
958 hscx->ip->name, hscx->bch.nr, count); in hscx_empty_fifo()
[all …]
DmISDNinfineon.c117 struct _ioaddr hscx; member
242 card->ipac.hscx[0].bch.debug = debug; in _set_debug()
243 card->ipac.hscx[1].bch.debug = debug; in _set_debug()
273 IOFUNC_IO(IPAC, inf_hw, hscx.a.io)
275 IOFUNC_IND(IPAC, inf_hw, hscx.a.io)
277 IOFUNC_MEMIO(IPAC, inf_hw, u32, hscx.a.p)
566 hw->ipac.hscx[0].slot = 0x1f; in reset_inf()
567 hw->ipac.hscx[1].slot = 0x23; in reset_inf()
732 hw->hscx.mode = hw->cfg.mode; in setup_io()
733 hw->hscx.a.io.ale = (u32)hw->cfg.start + DIVA_HSCX_ALE; in setup_io()
[all …]

12