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Searched refs:htotal (Results 1 – 25 of 139) sorted by relevance

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/drivers/gpu/drm/panel/
Dpanel-simple.c396 .htotal = 800 + 0 + 255 + 0,
421 .htotal = 1024 + 156 + 8 + 156,
444 .htotal = 1280 + 119 + 32 + 21,
467 .htotal = 1366 + 20 + 70,
491 .htotal = 1366 + 40 + 40 + 32,
514 .htotal = 1366 + 48 + 32 + 20,
537 .htotal = 1920 + 172 + 80 + 60,
565 .htotal = 1024 + 160 + 4 + 156,
593 .htotal = 1366 + 58 + 58 + 58,
616 .htotal = 1366 + 48 + 32 + 20,
[all …]
/drivers/gpu/drm/msm/mdp/mdp4/
Dmdp4_dsi_encoder.c65 mode->hsync_end, mode->htotal, in mdp4_dsi_encoder_mode_set()
79 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_dsi_encoder_mode_set()
80 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dsi_encoder_mode_set()
82 vsync_period = mode->vtotal * mode->htotal; in mdp4_dsi_encoder_mode_set()
83 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp4_dsi_encoder_mode_set()
84 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dsi_hsync_skew; in mdp4_dsi_encoder_mode_set()
85 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dsi_hsync_s… in mdp4_dsi_encoder_mode_set()
89 MDP4_DSI_HSYNC_CTRL_PERIOD(mode->htotal)); in mdp4_dsi_encoder_mode_set()
Dmdp4_dtv_encoder.c112 mode->hsync_end, mode->htotal, in mdp4_dtv_encoder_mode_set()
130 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_dtv_encoder_mode_set()
131 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dtv_encoder_mode_set()
133 vsync_period = mode->vtotal * mode->htotal; in mdp4_dtv_encoder_mode_set()
134 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp4_dtv_encoder_mode_set()
135 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; in mdp4_dtv_encoder_mode_set()
136 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_s… in mdp4_dtv_encoder_mode_set()
140 MDP4_DTV_HSYNC_CTRL_PERIOD(mode->htotal)); in mdp4_dtv_encoder_mode_set()
Dmdp4_lcdc_encoder.c280 mode->hsync_end, mode->htotal, in mdp4_lcdc_encoder_mode_set()
298 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_lcdc_encoder_mode_set()
299 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_lcdc_encoder_mode_set()
301 vsync_period = mode->vtotal * mode->htotal; in mdp4_lcdc_encoder_mode_set()
302 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp4_lcdc_encoder_mode_set()
303 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + lcdc_hsync_skew; in mdp4_lcdc_encoder_mode_set()
304 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + lcdc_hsync_… in mdp4_lcdc_encoder_mode_set()
308 MDP4_LCDC_HSYNC_CTRL_PERIOD(mode->htotal)); in mdp4_lcdc_encoder_mode_set()
/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5_encoder.c136 mode->hsync_end, mode->htotal, in mdp5_encoder_mode_set()
176 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp5_encoder_mode_set()
177 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp5_encoder_mode_set()
179 vsync_period = mode->vtotal * mode->htotal; in mdp5_encoder_mode_set()
180 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp5_encoder_mode_set()
181 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; in mdp5_encoder_mode_set()
182 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_s… in mdp5_encoder_mode_set()
190 display_v_start += mode->htotal - mode->hsync_start; in mdp5_encoder_mode_set()
198 MDP5_INTF_HSYNC_CTL_PERIOD(mode->htotal)); in mdp5_encoder_mode_set()
/drivers/gpu/drm/
Ddrm_modes.c56 mode->hsync_end, mode->htotal, in drm_mode_debug_printmodeline()
282 drm_mode->htotal = drm_mode->hdisplay + hblank; in drm_cvt_mode()
285 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; in drm_cvt_mode()
316 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; in drm_cvt_mode()
325 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; in drm_cvt_mode()
511 drm_mode->htotal = total_pixels; in drm_gtf_mode_complex()
592 dmode->htotal = dmode->hsync_end + vm->hback_porch; in drm_display_mode_from_videomode()
633 vm->hback_porch = dmode->htotal - dmode->hsync_end; in drm_display_mode_to_videomode()
756 if (mode->htotal < 0) in drm_mode_hsync()
759 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ in drm_mode_hsync()
[all …]
/drivers/media/i2c/
Dths8200.c61 static inline unsigned htotal(const struct v4l2_bt_timings *t) in htotal() function
252 ths8200_write(sd, THS8200_DTG1_SPEC_G_LSB, (htotal(bt)/2) & 0xff); in ths8200_setup()
254 ((htotal(bt)/2) >> 8) & 0x0f); in ths8200_setup()
257 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_MSB, htotal(bt) >> 8); in ths8200_setup()
258 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_LSB, htotal(bt) & 0xff); in ths8200_setup()
308 (htotal(bt) >> 8) & 0x1f); in ths8200_setup()
309 ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt)); in ths8200_setup()
356 "vertical: sync %d\n", __func__, htotal(bt), vtotal(bt), in ths8200_setup()
/drivers/video/fbdev/core/
Dfbmon.c721 int vtotal, htotal; in fb_get_monitor_limits() local
733 htotal = mode->xres + mode->right_margin + mode->hsync_len in fb_get_monitor_limits()
744 hscan = (pixclock + htotal / 2) / htotal; in fb_get_monitor_limits()
1112 u32 htotal; member
1244 timings->htotal = timings->hactive + timings->hblank; in fb_timings_vfreq()
1245 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_vfreq()
1255 timings->htotal = timings->hactive + timings->hblank; in fb_timings_hfreq()
1256 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_hfreq()
1263 timings->htotal = timings->hactive + timings->hblank; in fb_timings_dclk()
1264 timings->hfreq = timings->dclk/timings->htotal; in fb_timings_dclk()
[all …]
Dfbcvt.c44 u32 htotal; member
132 hsync = (FB_CVT_CELLSIZE * cvt->htotal)/100; in fb_cvt_hsync()
177 pixclock = (cvt->f_refresh * cvt->vtotal * cvt->htotal)/1000; in fb_cvt_pixclock()
179 pixclock = (cvt->htotal * 1000000)/cvt->hperiod; in fb_cvt_pixclock()
365 cvt.htotal = cvt.active_pixels + cvt.hblank; in fb_find_mode_cvt()
368 cvt.hfreq = cvt.pixclock/cvt.htotal; in fb_find_mode_cvt()
/drivers/gpu/drm/i915/
Dintel_tv.c345 int hsync_end, hblank_start, hblank_end, htotal; member
414 .hblank_start = 836, .htotal = 857,
456 .hblank_start = 836, .htotal = 857,
499 .hblank_start = 836, .htotal = 857,
542 .hblank_start = 836, .htotal = 857,
585 .hblank_start = 844, .htotal = 863,
630 .hblank_start = 844, .htotal = 863,
672 .hblank_start = 842, .htotal = 857,
696 .hblank_start = 859, .htotal = 863,
720 .hblank_start = 1580, .htotal = 1649,
[all …]
/drivers/video/fbdev/matrox/
Dmatroxfb_maven.c225 unsigned int htotal, unsigned int vtotal, in matroxfb_PLL_mavenclock() argument
238 scrlen = htotal * (vtotal - 1); in matroxfb_PLL_mavenclock()
239 fwant = htotal * vtotal; in matroxfb_PLL_mavenclock()
243 fwant, fxtal, htotal, vtotal, fmax); in matroxfb_PLL_mavenclock()
276 if (ln > htotal) in matroxfb_PLL_mavenclock()
298 unsigned int htotal, unsigned int vtotal, in matroxfb_mavenclock() argument
304 fvco = matroxfb_PLL_mavenclock(&maven1000_pll, ctl, htotal, vtotal, in, feed, &p, htotal2); in matroxfb_mavenclock()
747 m->htotal = h - 2; in maven_find_exact_clocks()
800 m->regs[0xA0] = m->htotal; in maven_compute_timming()
801 m->regs[0xA1] = m->htotal >> 8; in maven_compute_timming()
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/drivers/gpu/drm/cirrus/
Dcirrus_mode.c188 int hsyncstart, hsyncend, htotal, hdispend; in cirrus_crtc_mode_set() local
193 htotal = mode->htotal / 8; in cirrus_crtc_mode_set()
204 htotal -= 5; in cirrus_crtc_mode_set()
210 WREG_CRT(VGA_CRTC_H_TOTAL, htotal); in cirrus_crtc_mode_set()
242 if ((htotal + 5) & 64) in cirrus_crtc_mode_set()
244 if ((htotal + 5) & 128) in cirrus_crtc_mode_set()
/drivers/gpu/drm/gma500/
Dmdfld_device.c200 pipe->htotal = PSB_RVDC32(map->htotal); in mdfld_save_display_registers()
326 PSB_WVDC32(pipe->htotal, map->htotal); in mdfld_restore_display_registers()
455 .htotal = HTOTAL_A,
477 .htotal = HTOTAL_B,
500 .htotal = HTOTAL_C,
Dmdfld_tpo_vid.c50 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | in tpo_vid_get_config_mode()
66 dev_dbg(dev->dev, "htotal is %d\n", mode->htotal); in tpo_vid_get_config_mode()
76 mode->htotal = 887; in tpo_vid_get_config_mode()
Dmdfld_tmd_vid.c53 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \ in tmd_vid_get_config_mode()
69 dev_dbg(dev->dev, "htotal is %d\n", mode->htotal); in tmd_vid_get_config_mode()
79 mode->htotal = 499; in tmd_vid_get_config_mode()
/drivers/gpu/drm/msm/hdmi/
Dhdmi_bridge.c155 hstart = mode->htotal - mode->hsync_start; in msm_hdmi_bridge_mode_set()
156 hend = mode->htotal - mode->hsync_start + mode->hdisplay; in msm_hdmi_bridge_mode_set()
162 mode->htotal, mode->vtotal, hstart, hend, vstart, vend); in msm_hdmi_bridge_mode_set()
165 HDMI_TOTAL_H_TOTAL(mode->htotal - 1) | in msm_hdmi_bridge_mode_set()
/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Drootnv04.c60 args->v0.htotal = nvkm_rd32(device, 0x680824 + hoff) & 0xffff; in nv04_disp_scanoutpos()
61 args->v0.hblanke = args->v0.htotal - 1; in nv04_disp_scanoutpos()
68 if (!args->v0.vtotal || !args->v0.htotal) in nv04_disp_scanoutpos()
/drivers/video/fbdev/
Damifb.c755 u_short htotal; /* vmode */ member
1021 #define htotal2hw(htotal) (div8(htotal) - 1) argument
1025 #define hcenter2hw(htotal) (div8(htotal)) argument
1127 u_int htotal, vtotal; in ami_decode_var() local
1216 par->htotal = down8((var->left_margin + par->xres + var->right_margin + in ami_decode_var()
1227 par->diwstop_h = par->htotal - in ami_decode_var()
1238 if (par->diwstop_h >= par->htotal + 8) { in ami_decode_var()
1261 if (par->htotal != PAL_HTOTAL) { in ami_decode_var()
1273 htotal = PAL_HTOTAL>>clk_shift; in ami_decode_var()
1291 if (par->htotal != NTSC_HTOTAL) { in ami_decode_var()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c415 u32 htotal = nvkm_rdvgac(device, 0, 0x06); in nv04_devinit_preinit() local
416 htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x01) << 8; in nv04_devinit_preinit()
417 htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x20) << 4; in nv04_devinit_preinit()
418 htotal |= (nvkm_rdvgac(device, 0, 0x25) & 0x01) << 10; in nv04_devinit_preinit()
419 htotal |= (nvkm_rdvgac(device, 0, 0x41) & 0x01) << 11; in nv04_devinit_preinit()
420 if (!htotal) { in nv04_devinit_preinit()
/drivers/video/fbdev/geode/
Ddisplay_gx.c65 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal; in gx_set_mode() local
138 htotal = hblankend; in gx_set_mode()
148 ((htotal - 1) << 16)); in gx_set_mode()
Ddisplay_gx1.c85 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal; in gx1_set_mode() local
156 htotal = hblankend; in gx1_set_mode()
165 val = (hactive - 1) | ((htotal - 1) << 16); in gx1_set_mode()
/drivers/video/fbdev/sis/
Dinitextlfb.c40 int *htotal, int *vtotal, unsigned char rateindex);
177 sisfb_gettotalfrommode(struct SiS_Private *SiS_Pr, unsigned char modeno, int *htotal, in sisfb_gettotalfrommode() argument
214 *htotal = (((cr_data & 0xff) | ((unsigned short) (sr_data & 0x03) << 8)) + 5) * 8; in sisfb_gettotalfrommode()
/drivers/gpu/drm/mgag200/
Dmgag200_mode.c883 int hdisplay, hsyncstart, hsyncend, htotal; in mga_crtc_mode_set() local
1009 htotal = mode->htotal / 8 - 1; in mga_crtc_mode_set()
1012 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) in mga_crtc_mode_set()
1013 htotal++; in mga_crtc_mode_set()
1030 WREG_CRT(0, htotal - 4); in mga_crtc_mode_set()
1033 WREG_CRT(3, (htotal & 0x1F) | 0x80); in mga_crtc_mode_set()
1035 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F)); in mga_crtc_mode_set()
1069 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) | in mga_crtc_mode_set()
1072 (htotal & 0x40); in mga_crtc_mode_set()
1560 if (!mode->htotal || !mode->vtotal || !mode->clock) in mga_vga_calculate_mode_bandwidth()
[all …]
/drivers/gpu/drm/bridge/adv7511/
Dadv7533.c51 hbp = mode->htotal - mode->hsync_end; in adv7511_dsi_config_timing_gen()
61 regmap_write(adv->regmap_cec, 0x28, mode->htotal >> 4); in adv7511_dsi_config_timing_gen()
62 regmap_write(adv->regmap_cec, 0x29, (mode->htotal << 4) & 0xff); in adv7511_dsi_config_timing_gen()
/drivers/gpu/drm/exynos/
Dexynos_hdmi.c1204 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); in hdmi_v13_mode_apply()
1206 (m->htotal << 12) | m->vtotal); in hdmi_v13_mode_apply()
1244 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay)); in hdmi_v13_mode_apply()
1245 val |= ((m->htotal / 2) + in hdmi_v13_mode_apply()
1272 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal); in hdmi_v13_mode_apply()
1273 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay); in hdmi_v13_mode_apply()
1282 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); in hdmi_v14_mode_apply()
1284 hdmi_reg_writev(hdata, HDMI_H_LINE_0, 2, m->htotal); in hdmi_v14_mode_apply()
1315 (m->htotal / 2) + (m->hsync_start - m->hdisplay)); in hdmi_v14_mode_apply()
1317 (m->htotal / 2) + (m->hsync_start - m->hdisplay)); in hdmi_v14_mode_apply()
[all …]

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