| /drivers/i2c/muxes/ |
| D | i2c-mux-gpio.c | 142 unsigned initial_state, gpio_base; in i2c_mux_gpio_probe() local
195 initial_state = mux->data.idle; in i2c_mux_gpio_probe()
198 initial_state = mux->data.values[0]; in i2c_mux_gpio_probe()
213 initial_state & (1 << i)); in i2c_mux_gpio_probe()
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| /drivers/gpu/drm/radeon/ |
| D | rv730_dpm.c | 323 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); in rv730_populate_smc_initial_state() local
343 cpu_to_be32(initial_state->low.mclk); in rv730_populate_smc_initial_state()
357 cpu_to_be32(initial_state->low.sclk); in rv730_populate_smc_initial_state()
362 rv770_get_seq_value(rdev, &initial_state->low); in rv730_populate_smc_initial_state()
365 initial_state->low.vddc, in rv730_populate_smc_initial_state()
380 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in rv730_populate_smc_initial_state()
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| D | cypress_dpm.c | 1238 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_initial_state); in cypress_populate_smc_initial_state() local
1262 cpu_to_be32(initial_state->low.mclk); in cypress_populate_smc_initial_state()
1276 cpu_to_be32(initial_state->low.sclk); in cypress_populate_smc_initial_state()
1284 initial_state->low.vddc, in cypress_populate_smc_initial_state()
1290 initial_state->low.vddci, in cypress_populate_smc_initial_state()
1306 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in cypress_populate_smc_initial_state()
1314 initial_state->low.mclk); in cypress_populate_smc_initial_state()
1316 if (initial_state->low.mclk > pi->mclk_edc_enable_threshold) in cypress_populate_smc_initial_state()
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| D | rv770_dpm.c | 1027 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); in rv770_populate_smc_initial_state() local
1050 cpu_to_be32(initial_state->low.mclk); in rv770_populate_smc_initial_state()
1064 cpu_to_be32(initial_state->low.sclk); in rv770_populate_smc_initial_state()
1069 rv770_get_seq_value(rdev, &initial_state->low); in rv770_populate_smc_initial_state()
1072 initial_state->low.vddc, in rv770_populate_smc_initial_state()
1086 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in rv770_populate_smc_initial_state()
1093 if (initial_state->low.mclk <= pi->mclk_strobe_mode_threshold) in rv770_populate_smc_initial_state()
1095 rv740_get_mclk_frequency_ratio(initial_state->low.mclk) | 0x10; in rv770_populate_smc_initial_state()
1099 if (initial_state->low.mclk >= pi->mclk_edc_enable_threshold) in rv770_populate_smc_initial_state()
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| D | ni_dpm.c | 1683 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); in ni_populate_smc_initial_state() local
1707 cpu_to_be32(initial_state->performance_levels[0].mclk); in ni_populate_smc_initial_state()
1722 cpu_to_be32(initial_state->performance_levels[0].sclk); in ni_populate_smc_initial_state()
1729 initial_state->performance_levels[0].vddc, in ni_populate_smc_initial_state()
1746 initial_state->performance_levels[0].vddci, in ni_populate_smc_initial_state()
1764 initial_state->performance_levels[0].mclk); in ni_populate_smc_initial_state()
1766 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in ni_populate_smc_initial_state()
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| D | si_dpm.c | 4424 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); in si_populate_smc_initial_state() local
4451 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4467 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state()
4475 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4493 initial_state->performance_levels[0].vddci, in si_populate_smc_initial_state()
4499 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4500 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state()
4501 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4516 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4518 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
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| /drivers/video/fbdev/riva/ |
| D | rivafb.h | 50 struct riva_regs initial_state; /* initial startup video mode */ member
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| D | fbdev.c | 1050 riva_save_state(par, &par->initial_state); in rivafb_open()
1070 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext); in rivafb_release()
1071 riva_load_state(par, &par->initial_state); in rivafb_release()
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| /drivers/net/irda/ |
| D | sir_dev.c | 286 int sirdev_schedule_request(struct sir_dev *dev, int initial_state, unsigned param) in sirdev_schedule_request() argument
291 initial_state, param); in sirdev_schedule_request()
311 fsm->state = initial_state; in sirdev_schedule_request()
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| /drivers/scsi/isci/ |
| D | isci.h | 537 u32 initial_state);
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| D | host.c | 150 const struct sci_base_state *state_table, u32 initial_state) in sci_init_sm() argument
154 sm->initial_state_id = initial_state; in sci_init_sm()
155 sm->previous_state_id = initial_state; in sci_init_sm()
156 sm->current_state_id = initial_state; in sci_init_sm()
159 handler = sm->state_table[initial_state].enter_state; in sci_init_sm()
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| /drivers/video/fbdev/nvidia/ |
| D | nv_type.h | 98 RIVA_HW_STATE initial_state; member
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| D | nvidia.c | 1000 nvidia_save_vga(par, &par->initial_state); in nvidiafb_open()
1018 nvidia_write_regs(par, &par->initial_state); in nvidiafb_release()
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| /drivers/nvdimm/ |
| D | btt.c | 520 bool idx_set = false, initial_state = true; in log_set_indices() local
584 initial_state = false; in log_set_indices()
588 if (!initial_state && !idx_set) in log_set_indices()
595 if (initial_state) in log_set_indices()
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| /drivers/regulator/ |
| D | of_regulator.c | 167 constraints->initial_state = PM_SUSPEND_MEM; in of_get_regulation_constraints()
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| D | core.c | 1069 if (rdev->constraints->initial_state) { in set_machine_constraints()
1070 ret = suspend_prepare(rdev, rdev->constraints->initial_state); in set_machine_constraints()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | si_dpm.c | 4907 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state); in si_populate_smc_initial_state() local
4934 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4950 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state()
4958 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4976 initial_state->performance_levels[0].vddci, in si_populate_smc_initial_state()
4982 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4983 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state()
4984 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4997 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4999 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
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