| /drivers/net/ethernet/cisco/enic/ |
| D | vnic_intr.c | 30 void vnic_intr_free(struct vnic_intr *intr) in vnic_intr_free() argument
32 intr->ctrl = NULL; in vnic_intr_free()
35 int vnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr, in vnic_intr_alloc() argument
38 intr->index = index; in vnic_intr_alloc()
39 intr->vdev = vdev; in vnic_intr_alloc()
41 intr->ctrl = vnic_dev_get_res(vdev, RES_TYPE_INTR_CTRL, index); in vnic_intr_alloc()
42 if (!intr->ctrl) { in vnic_intr_alloc()
51 void vnic_intr_init(struct vnic_intr *intr, u32 coalescing_timer, in vnic_intr_init() argument
54 vnic_intr_coalescing_timer_set(intr, coalescing_timer); in vnic_intr_init()
55 iowrite32(coalescing_type, &intr->ctrl->coalescing_type); in vnic_intr_init()
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| D | vnic_intr.h | 54 static inline void vnic_intr_unmask(struct vnic_intr *intr) in vnic_intr_unmask() argument
56 iowrite32(0, &intr->ctrl->mask); in vnic_intr_unmask()
59 static inline void vnic_intr_mask(struct vnic_intr *intr) in vnic_intr_mask() argument
61 iowrite32(1, &intr->ctrl->mask); in vnic_intr_mask()
64 static inline int vnic_intr_masked(struct vnic_intr *intr) in vnic_intr_masked() argument
66 return ioread32(&intr->ctrl->mask); in vnic_intr_masked()
69 static inline void vnic_intr_return_credits(struct vnic_intr *intr, in vnic_intr_return_credits() argument
79 iowrite32(int_credit_return, &intr->ctrl->int_credit_return); in vnic_intr_return_credits()
82 static inline unsigned int vnic_intr_credits(struct vnic_intr *intr) in vnic_intr_credits() argument
84 return ioread32(&intr->ctrl->int_credits); in vnic_intr_credits()
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| D | enic_main.c | 337 vnic_intr_mask(&enic->intr[io_intr]); in enic_isr_legacy()
341 vnic_intr_unmask(&enic->intr[io_intr]); in enic_isr_legacy()
347 vnic_intr_return_all_credits(&enic->intr[notify_intr]); in enic_isr_legacy()
351 vnic_intr_return_all_credits(&enic->intr[err_intr]); in enic_isr_legacy()
361 vnic_intr_unmask(&enic->intr[io_intr]); in enic_isr_legacy()
403 unsigned int intr = enic_msix_err_intr(enic); in enic_isr_msix_err() local
405 vnic_intr_return_all_credits(&enic->intr[intr]); in enic_isr_msix_err()
417 unsigned int intr = enic_msix_notify_intr(enic); in enic_isr_msix_notify() local
420 vnic_intr_return_all_credits(&enic->intr[intr]); in enic_isr_msix_notify()
1224 unsigned int intr = enic_msix_rq_intr(enic, rq->index); in enic_set_int_moderation() local
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| D | enic.h | 183 ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX]; member
271 static inline bool enic_is_err_intr(struct enic *enic, int intr) in enic_is_err_intr() argument
275 return intr == enic_legacy_err_intr(); in enic_is_err_intr()
277 return intr == enic_msix_err_intr(enic); in enic_is_err_intr()
284 static inline bool enic_is_notify_intr(struct enic *enic, int intr) in enic_is_notify_intr() argument
288 return intr == enic_legacy_notify_intr(); in enic_is_notify_intr()
290 return intr == enic_msix_notify_intr(enic); in enic_is_notify_intr()
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| /drivers/scsi/snic/ |
| D | vnic_intr.c | 26 void svnic_intr_free(struct vnic_intr *intr) in svnic_intr_free() argument
28 intr->ctrl = NULL; in svnic_intr_free()
31 int svnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr, in svnic_intr_alloc() argument
34 intr->index = index; in svnic_intr_alloc()
35 intr->vdev = vdev; in svnic_intr_alloc()
37 intr->ctrl = svnic_dev_get_res(vdev, RES_TYPE_INTR_CTRL, index); in svnic_intr_alloc()
38 if (!intr->ctrl) { in svnic_intr_alloc()
47 void svnic_intr_init(struct vnic_intr *intr, unsigned int coalescing_timer, in svnic_intr_init() argument
50 iowrite32(coalescing_timer, &intr->ctrl->coalescing_timer); in svnic_intr_init()
51 iowrite32(coalescing_type, &intr->ctrl->coalescing_type); in svnic_intr_init()
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| D | vnic_intr.h | 54 svnic_intr_unmask(struct vnic_intr *intr) in svnic_intr_unmask() argument
56 iowrite32(0, &intr->ctrl->mask); in svnic_intr_unmask()
60 svnic_intr_mask(struct vnic_intr *intr) in svnic_intr_mask() argument
62 iowrite32(1, &intr->ctrl->mask); in svnic_intr_mask()
66 svnic_intr_return_credits(struct vnic_intr *intr, in svnic_intr_return_credits() argument
78 iowrite32(int_credit_return, &intr->ctrl->int_credit_return); in svnic_intr_return_credits()
82 svnic_intr_credits(struct vnic_intr *intr) in svnic_intr_credits() argument
84 return ioread32(&intr->ctrl->int_credits); in svnic_intr_credits()
88 svnic_intr_return_all_credits(struct vnic_intr *intr) in svnic_intr_return_all_credits() argument
90 unsigned int credits = svnic_intr_credits(intr); in svnic_intr_return_all_credits()
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| /drivers/scsi/fnic/ |
| D | vnic_intr.c | 27 void vnic_intr_free(struct vnic_intr *intr) in vnic_intr_free() argument
29 intr->ctrl = NULL; in vnic_intr_free()
32 int vnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr, in vnic_intr_alloc() argument
35 intr->index = index; in vnic_intr_alloc()
36 intr->vdev = vdev; in vnic_intr_alloc()
38 intr->ctrl = vnic_dev_get_res(vdev, RES_TYPE_INTR_CTRL, index); in vnic_intr_alloc()
39 if (!intr->ctrl) { in vnic_intr_alloc()
48 void vnic_intr_init(struct vnic_intr *intr, unsigned int coalescing_timer, in vnic_intr_init() argument
51 iowrite32(coalescing_timer, &intr->ctrl->coalescing_timer); in vnic_intr_init()
52 iowrite32(coalescing_type, &intr->ctrl->coalescing_type); in vnic_intr_init()
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| D | vnic_intr.h | 68 static inline void vnic_intr_unmask(struct vnic_intr *intr) in vnic_intr_unmask() argument
70 iowrite32(0, &intr->ctrl->mask); in vnic_intr_unmask()
73 static inline void vnic_intr_mask(struct vnic_intr *intr) in vnic_intr_mask() argument
75 iowrite32(1, &intr->ctrl->mask); in vnic_intr_mask()
78 static inline void vnic_intr_return_credits(struct vnic_intr *intr, in vnic_intr_return_credits() argument
88 iowrite32(int_credit_return, &intr->ctrl->int_credit_return); in vnic_intr_return_credits()
91 static inline unsigned int vnic_intr_credits(struct vnic_intr *intr) in vnic_intr_credits() argument
93 return ioread32(&intr->ctrl->int_credits); in vnic_intr_credits()
96 static inline void vnic_intr_return_all_credits(struct vnic_intr *intr) in vnic_intr_return_all_credits() argument
98 unsigned int credits = vnic_intr_credits(intr); in vnic_intr_return_all_credits()
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| /drivers/gpu/drm/nouveau/nvkm/engine/ce/ |
| D | gp100.c | 66 u32 intr = nvkm_rd32(device, 0x104410 + base) & mask; in gp100_ce_intr() local
67 if (intr & 0x00000001) { //XXX: guess in gp100_ce_intr()
70 intr &= ~0x00000001; in gp100_ce_intr()
72 if (intr & 0x00000002) { //XXX: guess in gp100_ce_intr()
75 intr &= ~0x00000002; in gp100_ce_intr()
77 if (intr & 0x00000004) { in gp100_ce_intr()
80 intr &= ~0x00000004; in gp100_ce_intr()
82 if (intr) { in gp100_ce_intr()
83 nvkm_warn(subdev, "intr %08x\n", intr); in gp100_ce_intr()
84 nvkm_wr32(device, 0x104410 + base, intr); in gp100_ce_intr()
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| D | gk104.c | 65 u32 intr = nvkm_rd32(device, 0x104908 + base) & mask; in gk104_ce_intr() local
66 if (intr & 0x00000001) { in gk104_ce_intr()
69 intr &= ~0x00000001; in gk104_ce_intr()
71 if (intr & 0x00000002) { in gk104_ce_intr()
74 intr &= ~0x00000002; in gk104_ce_intr()
76 if (intr & 0x00000004) { in gk104_ce_intr()
79 intr &= ~0x00000004; in gk104_ce_intr()
81 if (intr) { in gk104_ce_intr()
82 nvkm_warn(subdev, "intr %08x\n", intr); in gk104_ce_intr()
83 nvkm_wr32(device, 0x104908 + base, intr); in gk104_ce_intr()
[all …]
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| /drivers/net/wireless/zydas/zd1211rw/ |
| D | zd_usb.c | 373 struct zd_usb_interrupt *intr = &usb->intr; in handle_regs_int_override() local
375 spin_lock(&intr->lock); in handle_regs_int_override()
376 if (atomic_read(&intr->read_regs_enabled)) { in handle_regs_int_override()
377 atomic_set(&intr->read_regs_enabled, 0); in handle_regs_int_override()
378 intr->read_regs_int_overridden = 1; in handle_regs_int_override()
379 complete(&intr->read_regs.completion); in handle_regs_int_override()
381 spin_unlock(&intr->lock); in handle_regs_int_override()
387 struct zd_usb_interrupt *intr = &usb->intr; in handle_regs_int() local
392 spin_lock(&intr->lock); in handle_regs_int()
402 } else if (atomic_read(&intr->read_regs_enabled)) { in handle_regs_int()
[all …]
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| /drivers/irqchip/ |
| D | irq-mips-gic.c | 109 static inline void gic_reset_mask(unsigned int intr) in gic_reset_mask() argument
111 gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr), in gic_reset_mask()
112 1ul << GIC_INTR_BIT(intr)); in gic_reset_mask()
115 static inline void gic_set_mask(unsigned int intr) in gic_set_mask() argument
117 gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr), in gic_set_mask()
118 1ul << GIC_INTR_BIT(intr)); in gic_set_mask()
121 static inline void gic_set_polarity(unsigned int intr, unsigned int pol) in gic_set_polarity() argument
124 GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr), in gic_set_polarity()
125 (unsigned long)pol << GIC_INTR_BIT(intr)); in gic_set_polarity()
128 static inline void gic_set_trigger(unsigned int intr, unsigned int trig) in gic_set_trigger() argument
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| D | irq-mxs.c | 66 void __iomem *intr; member
88 return icoll_priv.intr + ((d->hwirq >> 2) * 0x10); in icoll_intr_reg()
105 icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); in icoll_mask_irq()
111 icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); in icoll_unmask_irq()
207 icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0; in icoll_of_init()
235 icoll_priv.intr = icoll_base + ASM9260_HW_ICOLL_INTERRUPT0; in asm9260_of_init()
245 writel(0, icoll_priv.intr + i); in asm9260_of_init()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/therm/ |
| D | g84.c | 145 uint32_t intr; in g84_therm_intr() local
149 intr = nvkm_rd32(device, 0x20100) & 0x3ff; in g84_therm_intr()
152 if (intr & 0x002) { in g84_therm_intr()
156 intr &= ~0x002; in g84_therm_intr()
160 if (intr & 0x004) { in g84_therm_intr()
164 intr &= ~0x004; in g84_therm_intr()
168 if (intr & 0x008) { in g84_therm_intr()
172 intr &= ~0x008; in g84_therm_intr()
176 if (intr & 0x010) { in g84_therm_intr()
180 intr &= ~0x010; in g84_therm_intr()
[all …]
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| /drivers/gpu/host1x/ |
| D | intr.c | 177 spin_lock(&syncpt->intr.lock); in process_wait_list()
179 remove_completed_waiters(&syncpt->intr.wait_head, threshold, in process_wait_list()
182 empty = list_empty(&syncpt->intr.wait_head); in process_wait_list()
186 reset_threshold_interrupt(host, &syncpt->intr.wait_head, in process_wait_list()
189 spin_unlock(&syncpt->intr.lock); in process_wait_list()
206 container_of(syncpt_intr, struct host1x_syncpt, intr); in syncpt_thresh_work()
239 spin_lock(&syncpt->intr.lock); in host1x_intr_add_action()
241 queue_was_empty = list_empty(&syncpt->intr.wait_head); in host1x_intr_add_action()
243 if (add_waiter_to_queue(waiter, &syncpt->intr.wait_head)) { in host1x_intr_add_action()
252 spin_unlock(&syncpt->intr.lock); in host1x_intr_add_action()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/mc/ |
| D | base.c | 44 for (map = mc->func->intr; !mask && map->stat; map++) { in nvkm_mc_intr_mask()
71 u32 intr = mc->func->intr_stat(mc); in nvkm_mc_intr_stat() local
72 if (WARN_ON_ONCE(intr == 0xffffffff)) in nvkm_mc_intr_stat()
73 intr = 0; /* likely fallen off the bus */ in nvkm_mc_intr_stat()
74 return intr; in nvkm_mc_intr_stat()
83 u32 stat, intr; in nvkm_mc_intr() local
89 intr = nvkm_mc_intr_stat(mc); in nvkm_mc_intr()
90 stat = nvkm_top_intr(device, intr, &subdevs); in nvkm_mc_intr()
99 for (map = mc->func->intr; map->stat; map++) { in nvkm_mc_intr()
100 if (intr & map->stat) { in nvkm_mc_intr()
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| D | gp100.c | 30 bool intr; member
38 u32 mask = mc->intr ? mc->mask : 0, i; in gp100_mc_intr_update()
51 mc->intr = false; in gp100_mc_intr_unarm()
62 mc->intr = true; in gp100_mc_intr_rearm()
68 gp100_mc_intr_mask(struct nvkm_mc *base, u32 mask, u32 intr) in gp100_mc_intr_mask() argument
73 mc->mask = (mc->mask & ~mask) | intr; in gp100_mc_intr_mask()
81 .intr = gk104_mc_intr,
100 mc->intr = false; in gp100_mc_new()
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| /drivers/scsi/ |
| D | mac53c94.c | 45 int intr; member
199 int nb, stat, seq, intr; in mac53c94_interrupt() local
208 intr = readb(®s->interrupt); in mac53c94_interrupt()
212 intr, stat, seq, state->phase); in mac53c94_interrupt()
215 if (intr & INTR_RESET) { in mac53c94_interrupt()
223 if (intr & INTR_ILL_CMD) { in mac53c94_interrupt()
225 intr, stat, seq, state->phase); in mac53c94_interrupt()
233 intr, stat, seq, state->phase); in mac53c94_interrupt()
249 if (intr & INTR_DISCONNECT) { in mac53c94_interrupt()
254 if (intr != INTR_BUS_SERV + INTR_DONE) { in mac53c94_interrupt()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/top/ |
| D | base.c | 37 info->intr = -1; in nvkm_top_device_new()
67 if (info->index == devidx && info->intr >= 0) in nvkm_top_intr_mask()
68 return BIT(info->intr); in nvkm_top_intr_mask()
76 nvkm_top_intr(struct nvkm_device *device, u32 intr, u64 *psubdevs) in nvkm_top_intr() argument
85 if (info->index != NVKM_SUBDEV_NR && info->intr >= 0) { in nvkm_top_intr()
86 if (intr & BIT(info->intr)) { in nvkm_top_intr()
88 handled |= BIT(info->intr); in nvkm_top_intr()
95 return intr & ~handled; in nvkm_top_intr()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/pmu/ |
| D | base.c | 151 u32 intr = nvkm_rd32(device, 0x10a008) & disp & ~(disp >> 16); in nvkm_pmu_intr() local
153 if (intr & 0x00000020) { in nvkm_pmu_intr()
160 intr &= ~0x00000020; in nvkm_pmu_intr()
164 if (intr & 0x00000040) { in nvkm_pmu_intr()
167 intr &= ~0x00000040; in nvkm_pmu_intr()
170 if (intr & 0x00000080) { in nvkm_pmu_intr()
175 intr &= ~0x00000080; in nvkm_pmu_intr()
178 if (intr) { in nvkm_pmu_intr()
179 nvkm_error(subdev, "intr %08x\n", intr); in nvkm_pmu_intr()
180 nvkm_wr32(device, 0x10a004, intr); in nvkm_pmu_intr()
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| /drivers/mtd/onenand/ |
| D | omap2.c | 93 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr) in wait_err() argument
96 msg, state, ctrl, intr); in wait_err()
100 unsigned int intr) in wait_warn() argument
103 "intr 0x%04x\n", msg, state, ctrl, intr); in wait_warn()
110 unsigned int intr = 0; in omap2_onenand_wait() local
134 intr = read_reg(c, ONENAND_REG_INTERRUPT); in omap2_onenand_wait()
135 if (intr & ONENAND_INT_MASTER) in omap2_onenand_wait()
140 wait_err("controller error", state, ctrl, intr); in omap2_onenand_wait()
143 if ((intr & intr_flags) == intr_flags) in omap2_onenand_wait()
166 intr = read_reg(c, ONENAND_REG_INTERRUPT); in omap2_onenand_wait()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| D | gf100.c | 232 u32 intr = nvkm_rd32(device, 0x00254c); in gf100_fifo_intr_sched() local
233 u32 code = intr & 0x000000ff; in gf100_fifo_intr_sched()
421 u32 intr = nvkm_rd32(device, 0x002a00); in gf100_fifo_intr_runlist() local
423 if (intr & 0x10000000) { in gf100_fifo_intr_runlist()
426 intr &= ~0x10000000; in gf100_fifo_intr_runlist()
429 if (intr) { in gf100_fifo_intr_runlist()
430 nvkm_error(subdev, "RUNLIST %08x\n", intr); in gf100_fifo_intr_runlist()
431 nvkm_wr32(device, 0x002a00, intr); in gf100_fifo_intr_runlist()
440 u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04)); in gf100_fifo_intr_engine_unit() local
444 nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr); in gf100_fifo_intr_engine_unit()
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| /drivers/gpu/drm/nouveau/nvkm/engine/ |
| D | falcon.c | 65 u32 intr = nvkm_rd32(device, base + 0x008) & dest & ~(dest >> 16); in nvkm_falcon_intr() local
72 if (intr & 0x00000040) { in nvkm_falcon_intr()
73 if (falcon->func->intr) { in nvkm_falcon_intr()
74 falcon->func->intr(falcon, chan); in nvkm_falcon_intr()
76 intr &= ~0x00000040; in nvkm_falcon_intr()
80 if (intr & 0x00000010) { in nvkm_falcon_intr()
83 intr &= ~0x00000010; in nvkm_falcon_intr()
86 if (intr) { in nvkm_falcon_intr()
87 nvkm_error(subdev, "intr %08x\n", intr); in nvkm_falcon_intr()
88 nvkm_wr32(device, base + 0x004, intr); in nvkm_falcon_intr()
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| /drivers/isdn/hisax/ |
| D | st5481_usb.c | 242 struct st5481_intr *intr = &adapter->intr; in st5481_setup_usb() local
299 intr->urb = urb; in st5481_setup_usb()
317 usb_free_urb(intr->urb); in st5481_setup_usb()
318 intr->urb = NULL; in st5481_setup_usb()
332 struct st5481_intr *intr = &adapter->intr; in st5481_release_usb() local
343 usb_kill_urb(intr->urb); in st5481_release_usb()
344 kfree(intr->urb->transfer_buffer); in st5481_release_usb()
345 usb_free_urb(intr->urb); in st5481_release_usb()
346 intr->urb = NULL; in st5481_release_usb()
371 struct st5481_intr *intr = &adapter->intr; in st5481_start() local
[all …]
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| /drivers/gpu/drm/msm/mdp/mdp5/ |
| D | mdp5_mdss.c | 53 u32 intr; in mdss_irq() local
55 intr = mdss_read(mdss, REG_MDSS_HW_INTR_STATUS); in mdss_irq()
57 VERB("intr=%08x", intr); in mdss_irq()
59 while (intr) { in mdss_irq()
60 irq_hw_number_t hwirq = fls(intr) - 1; in mdss_irq()
64 intr &= ~(1 << hwirq); in mdss_irq()
|