| /drivers/gpu/drm/msm/mdp/ |
| D | mdp_kms.c | 35 uint32_t irqmask = mdp_kms->vblank_mask; in update_irq() local
40 irqmask |= irq->irqmask; in update_irq()
42 mdp_kms->funcs->set_irqmask(mdp_kms, irqmask, mdp_kms->cur_irq_mask); in update_irq()
43 mdp_kms->cur_irq_mask = irqmask; in update_irq()
65 if (handler->irqmask & status) { in mdp_dispatch_irqs()
67 handler->irq(handler, handler->irqmask & status); in mdp_dispatch_irqs()
98 void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask) in mdp_irq_wait() argument
103 .irqmask = irqmask, in mdp_irq_wait()
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| D | mdp_kms.h | 33 void (*set_irqmask)(struct mdp_kms *mdp_kms, uint32_t irqmask,
70 uint32_t irqmask; member
77 void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask);
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| /drivers/gpu/drm/omapdrm/ |
| D | omap_irq.c | 35 uint32_t irqmask = priv->vblank_mask; in omap_irq_update() local
40 irqmask |= irq->irqmask; in omap_irq_update()
42 DBG("irqmask=%08x", irqmask); in omap_irq_update()
44 dispc_write_irqenable(irqmask); in omap_irq_update()
113 uint32_t irqmask, int count) in omap_irq_wait_init() argument
117 wait->irq.irqmask = irqmask; in omap_irq_wait_init()
210 if (handler->irqmask & irqstatus) { in omap_irq_handler()
212 handler->irq(handler, handler->irqmask & irqstatus); in omap_irq_handler()
245 error_handler->irqmask = DISPC_IRQ_OCP_ERR; in omap_drm_irq_install()
250 error_handler->irqmask &= ~DISPC_IRQ_SYNC_LOST_DIGIT; in omap_drm_irq_install()
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| D | omap_drv.h | 59 uint32_t irqmask; member
68 uint32_t irqmask, int count);
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| D | omap_crtc.c | 562 omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc); in omap_crtc_init()
565 omap_crtc->error_irq.irqmask = in omap_crtc_init()
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| /drivers/clocksource/ |
| D | timer-atmel-st.c | 34 static u32 irqmask; variable
66 sr &= irqmask; in at91rm9200_timer_interrupt()
121 irqmask = 0; in clkevt32k_shutdown()
122 regmap_write(regmap_st, AT91_ST_IER, irqmask); in clkevt32k_shutdown()
134 irqmask = AT91_ST_ALMS; in clkevt32k_set_oneshot()
136 regmap_write(regmap_st, AT91_ST_IER, irqmask); in clkevt32k_set_oneshot()
145 irqmask = AT91_ST_PITS; in clkevt32k_set_periodic()
147 regmap_write(regmap_st, AT91_ST_IER, irqmask); in clkevt32k_set_periodic()
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| /drivers/irqchip/ |
| D | irq-i8259.c | 114 int irqmask = 1 << irq; in i8259A_irq_real() local
118 value = inb(PIC_MASTER_CMD) & irqmask; in i8259A_irq_real()
123 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); in i8259A_irq_real()
136 unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE; in mask_and_ack_8259A() local
139 irqmask = 1 << irq; in mask_and_ack_8259A()
156 if (cached_irq_mask & irqmask) in mask_and_ack_8259A()
158 cached_irq_mask |= irqmask; in mask_and_ack_8259A()
191 if (!(spurious_irq_mask & irqmask)) { in mask_and_ack_8259A()
193 spurious_irq_mask |= irqmask; in mask_and_ack_8259A()
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| /drivers/gpu/drm/msm/mdp/mdp4/ |
| D | mdp4_irq.c | 22 void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, in mdp4_set_irqmask() argument
26 irqmask ^ (irqmask & old_irqmask)); in mdp4_set_irqmask()
27 mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_ENABLE, irqmask); in mdp4_set_irqmask()
51 error_handler->irqmask = MDP4_IRQ_PRIMARY_INTF_UDERRUN | in mdp4_irq_postinstall()
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| D | mdp4_crtc.c | 560 return mdp4_crtc->vblank.irqmask; in mdp4_crtc_vblank()
645 mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma); in mdp4_crtc_init()
648 mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma); in mdp4_crtc_init()
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| D | mdp4_kms.h | 171 void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
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| /drivers/gpu/drm/msm/mdp/mdp5/ |
| D | mdp5_irq.c | 23 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, in mdp5_set_irqmask() argument
27 irqmask ^ (irqmask & old_irqmask)); in mdp5_set_irqmask()
28 mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask); in mdp5_set_irqmask()
52 error_handler->irqmask = MDP5_IRQ_INTF0_UNDER_RUN | in mdp5_irq_postinstall()
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| D | mdp5_crtc.c | 708 return mdp5_crtc->vblank.irqmask; in mdp5_crtc_vblank()
719 mdp5_crtc->err.irqmask = intf2err(intf->num); in mdp5_crtc_set_pipeline()
720 mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf); in mdp5_crtc_set_pipeline()
724 mdp5_crtc->pp_done.irqmask = lm2ppdone(lm); in mdp5_crtc_set_pipeline()
728 mdp5_crtc->pp_done.irqmask = 0; in mdp5_crtc_set_pipeline()
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| D | mdp5_kms.h | 187 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
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| /drivers/regulator/ |
| D | lp8755.c | 50 unsigned int irqmask; member
374 && (pchip->irqmask & (0x04 << icnt)) in lp8755_irq_handler()
390 if ((flag1 & 0x01) && (pchip->irqmask & 0x01)) in lp8755_irq_handler()
398 if ((flag1 & 0x02) && (pchip->irqmask & 0x02)) in lp8755_irq_handler()
427 pchip->irqmask = regval; in lp8755_int_config()
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| /drivers/ata/ |
| D | pata_hpt3x2n.c | 494 u8 irqmask; in hpt3x2n_init_one() local
543 pci_read_config_byte(dev, 0x5A, &irqmask); in hpt3x2n_init_one()
544 irqmask &= ~0x10; in hpt3x2n_init_one()
545 pci_write_config_byte(dev, 0x5a, irqmask); in hpt3x2n_init_one()
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| D | pata_icside.c | 66 unsigned int irqmask; member
383 info->irqmask = 1; in pata_icside_register_v5()
444 ec->irqmask = info->irqmask; in pata_icside_add_ports()
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| D | pata_hpt37x.c | 826 u8 irqmask; in hpt37x_init_one() local
918 pci_read_config_byte(dev, 0x5A, &irqmask); in hpt37x_init_one()
919 irqmask &= ~0x10; in hpt37x_init_one()
920 pci_write_config_byte(dev, 0x5a, irqmask); in hpt37x_init_one()
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| /drivers/media/rc/ |
| D | winbond-cir.c | 212 u8 irqmask; member
277 wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask) in wbcir_set_irqmask() argument
279 if (data->irqmask == irqmask) in wbcir_set_irqmask()
283 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER); in wbcir_set_irqmask()
284 data->irqmask = irqmask; in wbcir_set_irqmask()
493 status &= data->irqmask; in wbcir_irq_handler()
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| /drivers/media/pci/tw5864/ |
| D | tw5864-core.c | 88 tw_writel(TW5864_INTR_ENABLE_L, dev->irqmask & 0xffff); in tw5864_irqmask_apply()
89 tw_writel(TW5864_INTR_ENABLE_H, (dev->irqmask >> 16)); in tw5864_irqmask_apply()
97 dev->irqmask = 0; in tw5864_interrupts_disable()
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| D | tw5864.h | 172 u32 irqmask; member
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | dispc-compat.h | 24 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
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| D | dispc-compat.c | 642 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, in omap_dispc_wait_for_irq_interruptible_timeout() argument
651 irqmask); in omap_dispc_wait_for_irq_interruptible_timeout()
659 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask); in omap_dispc_wait_for_irq_interruptible_timeout()
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| /drivers/net/ethernet/nvidia/ |
| D | forcedeth.c | 780 u32 irqmask; member
3572 if (np->irqmask != NVREG_IRQMASK_CPU) { in nv_change_interrupt_mode()
3573 np->irqmask = NVREG_IRQMASK_CPU; in nv_change_interrupt_mode()
3582 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) { in nv_change_interrupt_mode()
3583 np->irqmask = NVREG_IRQMASK_THROUGHPUT; in nv_change_interrupt_mode()
3605 if (!(np->events & np->irqmask)) in nv_nic_irq()
3638 if (!(np->events & np->irqmask)) in nv_nic_irq_optimized()
3667 if (!(events & np->irqmask)) in nv_nic_irq_tx()
3747 np->nic_poll_irq = np->irqmask; in nv_napi_poll()
3761 writel(np->irqmask, base + NvRegIrqMask); in nv_napi_poll()
[all …]
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| /drivers/media/pci/ivtv/ |
| D | ivtv-driver.c | 315 itv->irqmask &= ~mask; in ivtv_clear_irq_mask()
316 write_reg_sync(itv->irqmask, IVTV_REG_IRQMASK); in ivtv_clear_irq_mask()
321 itv->irqmask |= mask; in ivtv_set_irq_mask()
322 write_reg_sync(itv->irqmask, IVTV_REG_IRQMASK); in ivtv_set_irq_mask()
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| /drivers/mmc/host/ |
| D | mmci.c | 777 unsigned int datactrl, timeout, irqmask; in mmci_start_data() local
847 irqmask = MCI_RXFIFOHALFFULLMASK; in mmci_start_data()
855 irqmask |= MCI_RXDATAAVLBLMASK; in mmci_start_data()
861 irqmask = MCI_TXFIFOHALFEMPTYMASK; in mmci_start_data()
866 mmci_set_mask1(host, irqmask); in mmci_start_data()
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