| /drivers/staging/media/omap4iss/ |
| D | iss_csiphy.c | 40 reg |= (phy->lanes.data[i].pol ? in csiphy_lanes_config()
42 reg |= (phy->lanes.data[i].pos << in csiphy_lanes_config()
48 reg |= phy->lanes.clk.pol ? CSI2_COMPLEXIO_CFG_CLOCK_POL : 0; in csiphy_lanes_config()
49 reg |= phy->lanes.clk.pos << CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT; in csiphy_lanes_config()
127 struct iss_csiphy_lanes_cfg *lanes; in omap4iss_csiphy_config() local
132 lanes = &subdevs->bus.csi2.lanecfg; in omap4iss_csiphy_config()
179 if (lanes->data[i].pos == 0) in omap4iss_csiphy_config()
182 if (lanes->data[i].pol > 1 || in omap4iss_csiphy_config()
183 lanes->data[i].pos > (csi2->phy->max_data_lanes + 1)) in omap4iss_csiphy_config()
186 if (used_lanes & (1 << lanes->data[i].pos)) in omap4iss_csiphy_config()
[all …]
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| D | iss_csiphy.h | 41 struct iss_csiphy_lanes_cfg lanes; member
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| /drivers/media/platform/omap3isp/ |
| D | ispcsiphy.c | 170 struct isp_csiphy_lanes_cfg *lanes; in omap3isp_csiphy_config() local
185 lanes = &buscfg->bus.ccp2.lanecfg; in omap3isp_csiphy_config()
187 lanes = &buscfg->bus.csi2.lanecfg; in omap3isp_csiphy_config()
191 if (lanes->data[i].pol > 1 || lanes->data[i].pos > 3) in omap3isp_csiphy_config()
194 if (used_lanes & (1 << lanes->data[i].pos)) in omap3isp_csiphy_config()
197 used_lanes |= 1 << lanes->data[i].pos; in omap3isp_csiphy_config()
200 if (lanes->clk.pol > 1 || lanes->clk.pos > 3) in omap3isp_csiphy_config()
203 if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos)) in omap3isp_csiphy_config()
249 reg |= (lanes->data[i].pol << in omap3isp_csiphy_config()
251 reg |= (lanes->data[i].pos << in omap3isp_csiphy_config()
[all …]
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| /drivers/gpu/drm/bridge/adv7511/ |
| D | adv7533.c | 58 clock_div_by_lanes[dsi->lanes - 2] << 3); in adv7511_dsi_config_timing_gen()
89 regmap_write(adv->regmap_cec, 0x1c, dsi->lanes << 4); in adv7533_dsi_power_on()
121 int lanes, ret; in adv7533_mode_set() local
127 lanes = 4; in adv7533_mode_set()
129 lanes = 3; in adv7533_mode_set()
131 if (lanes != dsi->lanes) { in adv7533_mode_set()
133 dsi->lanes = lanes; in adv7533_mode_set()
206 dsi->lanes = adv->num_dsi_lanes; in adv7533_attach_dsi()
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | hdmi_common.c | 19 u32 lanes[8]; in hdmi_parse_lanes_of() local
21 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { in hdmi_parse_lanes_of()
26 r = of_property_read_u32_array(ep, "lanes", lanes, in hdmi_parse_lanes_of()
27 ARRAY_SIZE(lanes)); in hdmi_parse_lanes_of()
33 r = hdmi_phy_parse_lanes(phy, lanes); in hdmi_parse_lanes_of()
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| D | hdmi_phy.c | 42 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes) in hdmi_phy_parse_lanes() argument
50 dx = lanes[i]; in hdmi_phy_parse_lanes()
51 dy = lanes[i + 1]; in hdmi_phy_parse_lanes()
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| /drivers/gpu/drm/omapdrm/dss/ |
| D | hdmi_common.c | 19 u32 lanes[8]; in hdmi_parse_lanes_of() local
21 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { in hdmi_parse_lanes_of()
26 r = of_property_read_u32_array(ep, "lanes", lanes, in hdmi_parse_lanes_of()
27 ARRAY_SIZE(lanes)); in hdmi_parse_lanes_of()
33 r = hdmi_phy_parse_lanes(phy, lanes); in hdmi_parse_lanes_of()
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| D | hdmi_phy.c | 43 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes) in hdmi_phy_parse_lanes() argument
51 dx = lanes[i]; in hdmi_phy_parse_lanes()
52 dy = lanes[i + 1]; in hdmi_phy_parse_lanes()
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| /drivers/phy/tegra/ |
| D | xusb.c | 43 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
46 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
47 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
102 return of_find_node_by_name(np, pad->soc->lanes[index].name); in tegra_xusb_pad_find_phy_node()
202 pad->lanes = devm_kcalloc(&pad->dev, pad->soc->num_lanes, sizeof(lane), in tegra_xusb_pad_register()
204 if (!pad->lanes) { in tegra_xusb_pad_register()
219 pad->lanes[i] = phy_create(&pad->dev, np, ops); in tegra_xusb_pad_register()
220 if (IS_ERR(pad->lanes[i])) { in tegra_xusb_pad_register()
221 err = PTR_ERR(pad->lanes[i]); in tegra_xusb_pad_register()
228 phy_destroy(pad->lanes[i]); in tegra_xusb_pad_register()
[all …]
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| D | xusb.h | 141 const struct tegra_xusb_lane_soc *lanes; member
151 struct phy **lanes; member
387 struct list_head lanes; member
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| D | xusb-tegra124.c | 446 usb2->base.soc = &pad->soc->lanes[index]; in tegra124_usb2_lane_probe()
670 .lanes = tegra124_usb2_lanes,
695 ulpi->base.soc = &pad->soc->lanes[index]; in tegra124_ulpi_lane_probe()
805 .lanes = tegra124_ulpi_lanes,
831 hsic->base.soc = &pad->soc->lanes[index]; in tegra124_hsic_lane_probe()
1021 .lanes = tegra124_hsic_lanes,
1051 pcie->base.soc = &pad->soc->lanes[index]; in tegra124_pcie_lane_probe()
1209 .lanes = tegra124_pcie_lanes,
1229 sata->base.soc = &pad->soc->lanes[index]; in tegra124_sata_lane_probe()
1405 .lanes = tegra124_sata_lanes,
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| /drivers/gpu/drm/hisilicon/kirin/ |
| D | dw_drm_dsi.c | 89 u32 lanes; member
331 u32 lanes) in dsi_set_phy_timer() argument
338 val = (lanes - 1) | (PHY_STOP_WAIT_TIME << 8); in dsi_set_phy_timer()
364 u32 lanes) in dsi_set_mipi_phy() argument
371 dsi_set_phy_timer(base, phy, lanes); in dsi_set_mipi_phy()
395 for (i = 0; i < lanes; i++) { in dsi_set_mipi_phy()
548 dphy_req_kHz = mode->clock * bpp / dsi->lanes; in dsi_mipi_init()
555 dsi_set_mipi_phy(base, phy, dsi->lanes); in dsi_mipi_init()
567 dsi->lanes, mode->clock, phy->lane_byte_clk_kHz); in dsi_mipi_init()
665 if (mdsi->lanes < 1 || mdsi->lanes > 4) { in dsi_host_attach()
[all …]
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| /drivers/gpu/drm/tegra/ |
| D | dsi.c | 39 unsigned int lanes; member
72 unsigned int lanes; member
491 return dsi->master->lanes + dsi->lanes; in tegra_dsi_get_lanes()
494 return dsi->lanes + dsi->slave->lanes; in tegra_dsi_get_lanes()
496 return dsi->lanes; in tegra_dsi_get_lanes()
529 DSI_CONTROL_LANES(dsi->lanes - 1) | in tegra_dsi_configure()
613 unsigned int lanes = state->lanes; in tegra_dsi_configure() local
617 delay = DIV_ROUND_UP(delay * mul, div * lanes); in tegra_dsi_configure()
621 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); in tegra_dsi_configure()
622 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); in tegra_dsi_configure()
[all …]
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| /drivers/nubus/ |
| D | nubus.c | 211 dir->mask = board->lanes; in nubus_get_root_dir()
222 dir->mask = dev->board->lanes; in nubus_get_func_dir()
234 dir->mask = board->lanes; in nubus_get_board_dir()
732 nubus_rewind(&rp, 4, board->lanes); in nubus_find_rom_dir()
733 if (nubus_get_rom(&rp, 4, board->lanes) != NUBUS_TEST_PATTERN) { in nubus_find_rom_dir()
738 board->lanes); in nubus_find_rom_dir()
747 nubus_rewind(&romdir, ROM_DIR_OFFSET, board->lanes); in nubus_find_rom_dir()
750 dir.mask = board->lanes; in nubus_find_rom_dir()
794 nubus_move(&board->directory, nubus_expand32(board->doffset), board->lanes); in nubus_find_rom_dir()
847 board->lanes = bytelanes; in nubus_add_board()
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| /drivers/gpu/drm/gma500/ |
| D | intel_bios.c | 102 switch (edp_link_params->lanes) { in parse_edp()
104 dev_priv->edp.lanes = 1; in parse_edp()
107 dev_priv->edp.lanes = 2; in parse_edp()
111 dev_priv->edp.lanes = 4; in parse_edp()
115 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); in parse_edp()
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| /drivers/media/i2c/ |
| D | tc358743.c | 686 unsigned lanes = tc358743_num_csi_lanes_needed(sd); in tc358743_set_csi() local
692 if (lanes < 1) in tc358743_set_csi()
694 if (lanes < 1) in tc358743_set_csi()
696 if (lanes < 2) in tc358743_set_csi()
698 if (lanes < 3) in tc358743_set_csi()
700 if (lanes < 4) in tc358743_set_csi()
714 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) | in tc358743_set_csi()
715 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) | in tc358743_set_csi()
716 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) | in tc358743_set_csi()
717 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) | in tc358743_set_csi()
[all …]
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| /drivers/pci/host/ |
| D | pci-xgene.c | 219 u32 *lanes, u32 *speed) in xgene_pcie_linkup() argument
229 *lanes = val32 >> 26; in xgene_pcie_linkup()
499 u32 val, lanes = 0, speed = 0; in xgene_pcie_setup() local
516 xgene_pcie_linkup(port, &lanes, &speed); in xgene_pcie_setup()
520 dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1); in xgene_pcie_setup()
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| D | pci-tegra.c | 314 unsigned int lanes; member
882 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_phy_power_on()
899 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_phy_power_off()
1221 port->phys = devm_kcalloc(dev, sizeof(phy), port->lanes, GFP_KERNEL); in tegra_pcie_port_get_phys()
1225 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_get_phys()
1606 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes, in tegra_pcie_get_xbar_config() argument
1613 switch (lanes) { in tegra_pcie_get_xbar_config()
1625 switch (lanes) { in tegra_pcie_get_xbar_config()
1642 switch (lanes) { in tegra_pcie_get_xbar_config()
1824 u32 lanes = 0, mask = 0; in tegra_pcie_parse_dt() local
[all …]
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| D | pcie-rockchip.c | 205 u32 lanes; member
491 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) | in rockchip_pcie_init_port()
793 rockchip->lanes = 1; in rockchip_pcie_parse_dt()
794 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes); in rockchip_pcie_parse_dt()
795 if (!err && (rockchip->lanes == 0 || in rockchip_pcie_parse_dt()
796 rockchip->lanes == 3 || in rockchip_pcie_parse_dt()
797 rockchip->lanes > 4)) { in rockchip_pcie_parse_dt()
799 rockchip->lanes = 1; in rockchip_pcie_parse_dt()
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| /drivers/gpu/drm/mediatek/ |
| D | mtk_dsi.c | 139 unsigned int lanes; member
243 overhead_bits = overhead_cycles * dsi->lanes * 8; in mtk_dsi_poweron()
247 htotal * dsi->lanes); in mtk_dsi_poweron()
379 switch (dsi->lanes) { in dsi_rxtx_control()
749 dsi->lanes = device->lanes; in mtk_dsi_host_attach()
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| /drivers/gpu/drm/panel/ |
| D | panel-simple.c | 1759 unsigned int lanes; member
1787 .lanes = 4,
1817 .lanes = 4,
1845 .lanes = 4,
1873 .lanes = 4,
1902 .lanes = 4,
1945 dsi->lanes = desc->lanes; in panel_simple_dsi_probe()
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| /drivers/gpu/drm/rockchip/ |
| D | dw-mipi-dsi.c | 285 u32 lanes; member
480 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9; in dw_mipi_dsi_get_lane_bps()
513 if (device->lanes > dsi->pdata->max_data_lanes) { in dw_mipi_dsi_host_attach()
515 device->lanes); in dw_mipi_dsi_host_attach()
525 dsi->lanes = device->lanes; in dw_mipi_dsi_host_attach()
806 N_LANES(dsi->lanes)); in dw_mipi_dsi_dphy_interface_config()
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| /drivers/pinctrl/tegra/ |
| D | pinctrl-tegra-xusb.c | 69 const struct tegra_xusb_padctl_lane *lanes; member
311 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinmux_set()
345 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinconf_group_get()
384 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinconf_group_set()
867 .lanes = tegra124_lanes,
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| /drivers/gpu/drm/msm/dsi/ |
| D | dsi_host.c | 163 unsigned int lanes; member
631 u8 lanes = msm_host->lanes; in dsi_calc_clk_rate() local
641 if (lanes > 0) { in dsi_calc_clk_rate()
642 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes); in dsi_calc_clk_rate()
840 DBG("lane number=%d", msm_host->lanes); in dsi_ctrl_config()
841 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); in dsi_ctrl_config()
1477 if (dsi->lanes > msm_host->num_data_lanes) in dsi_host_attach()
1481 msm_host->lanes = dsi->lanes; in dsi_host_attach()
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| /drivers/edac/ |
| D | ppc4xx_edac.c | 442 unsigned int lane, lanes; in ppc4xx_edac_generate_lane_message() local
455 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) { in ppc4xx_edac_generate_lane_message()
459 (lanes++ ? ", " : ""), lane); in ppc4xx_edac_generate_lane_message()
470 n = snprintf(buffer, size, "%s; ", lanes ? "" : "None"); in ppc4xx_edac_generate_lane_message()
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