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1 #ifndef _LMC_IOCTL_H_
2 #define _LMC_IOCTL_H_
3 /*	$Id: lmc_ioctl.h,v 1.15 2000/04/06 12:16:43 asj Exp $	*/
4 
5  /*
6   * Copyright (c) 1997-2000 LAN Media Corporation (LMC)
7   * All rights reserved.  www.lanmedia.com
8   *
9   * This code is written by:
10   * Andrew Stanley-Jones (asj@cban.com)
11   * Rob Braun (bbraun@vix.com),
12   * Michael Graff (explorer@vix.com) and
13   * Matt Thomas (matt@3am-software.com).
14   *
15   * This software may be used and distributed according to the terms
16   * of the GNU General Public License version 2, incorporated herein by reference.
17   */
18 
19 #define LMCIOCGINFO             SIOCDEVPRIVATE+3 /* get current state */
20 #define LMCIOCSINFO             SIOCDEVPRIVATE+4 /* set state to user values */
21 #define LMCIOCGETLMCSTATS       SIOCDEVPRIVATE+5
22 #define LMCIOCCLEARLMCSTATS     SIOCDEVPRIVATE+6
23 #define LMCIOCDUMPEVENTLOG      SIOCDEVPRIVATE+7
24 #define LMCIOCGETXINFO          SIOCDEVPRIVATE+8
25 #define LMCIOCSETCIRCUIT        SIOCDEVPRIVATE+9
26 #define LMCIOCUNUSEDATM         SIOCDEVPRIVATE+10
27 #define LMCIOCRESET             SIOCDEVPRIVATE+11
28 #define LMCIOCT1CONTROL         SIOCDEVPRIVATE+12
29 #define LMCIOCIFTYPE            SIOCDEVPRIVATE+13
30 #define LMCIOCXILINX            SIOCDEVPRIVATE+14
31 
32 #define LMC_CARDTYPE_UNKNOWN            -1
33 #define LMC_CARDTYPE_HSSI               1       /* probed card is a HSSI card */
34 #define LMC_CARDTYPE_DS3                2       /* probed card is a DS3 card */
35 #define LMC_CARDTYPE_SSI                3       /* probed card is a SSI card */
36 #define LMC_CARDTYPE_T1                 4       /* probed card is a T1 card */
37 
38 #define LMC_CTL_CARDTYPE_LMC5200	0	/* HSSI */
39 #define LMC_CTL_CARDTYPE_LMC5245	1	/* DS3 */
40 #define LMC_CTL_CARDTYPE_LMC1000	2	/* SSI, V.35 */
41 #define LMC_CTL_CARDTYPE_LMC1200        3       /* DS1 */
42 
43 #define LMC_CTL_OFF			0	/* generic OFF value */
44 #define LMC_CTL_ON			1	/* generic ON value */
45 
46 #define LMC_CTL_CLOCK_SOURCE_EXT	0	/* clock off line */
47 #define LMC_CTL_CLOCK_SOURCE_INT	1	/* internal clock */
48 
49 #define LMC_CTL_CRC_LENGTH_16		16
50 #define LMC_CTL_CRC_LENGTH_32		32
51 #define LMC_CTL_CRC_BYTESIZE_2          2
52 #define LMC_CTL_CRC_BYTESIZE_4          4
53 
54 
55 #define LMC_CTL_CABLE_LENGTH_LT_100FT	0	/* DS3 cable < 100 feet */
56 #define LMC_CTL_CABLE_LENGTH_GT_100FT	1	/* DS3 cable >= 100 feet */
57 
58 #define LMC_CTL_CIRCUIT_TYPE_E1 0
59 #define LMC_CTL_CIRCUIT_TYPE_T1 1
60 
61 /*
62  * IFTYPE defines
63  */
64 #define LMC_PPP         1               /* use generic HDLC interface */
65 #define LMC_NET         2               /* use direct net interface */
66 #define LMC_RAW         3               /* use direct net interface */
67 
68 /*
69  * These are not in the least IOCTL related, but I want them common.
70  */
71 /*
72  * assignments for the GPIO register on the DEC chip (common)
73  */
74 #define LMC_GEP_INIT		0x01 /* 0: */
75 #define LMC_GEP_RESET		0x02 /* 1: */
76 #define LMC_GEP_MODE		0x10 /* 4: */
77 #define LMC_GEP_DP		0x20 /* 5: */
78 #define LMC_GEP_DATA		0x40 /* 6: serial out */
79 #define LMC_GEP_CLK	        0x80 /* 7: serial clock */
80 
81 /*
82  * HSSI GPIO assignments
83  */
84 #define LMC_GEP_HSSI_ST		0x04 /* 2: receive timing sense (deprecated) */
85 #define LMC_GEP_HSSI_CLOCK	0x08 /* 3: clock source */
86 
87 /*
88  * T1 GPIO assignments
89  */
90 #define LMC_GEP_SSI_GENERATOR	0x04 /* 2: enable prog freq gen serial i/f */
91 #define LMC_GEP_SSI_TXCLOCK	0x08 /* 3: provide clock on TXCLOCK output */
92 
93 /*
94  * Common MII16 bits
95  */
96 #define LMC_MII16_LED0         0x0080
97 #define LMC_MII16_LED1         0x0100
98 #define LMC_MII16_LED2         0x0200
99 #define LMC_MII16_LED3         0x0400  /* Error, and the red one */
100 #define LMC_MII16_LED_ALL      0x0780  /* LED bit mask */
101 #define LMC_MII16_FIFO_RESET   0x0800
102 
103 /*
104  * definitions for HSSI
105  */
106 #define LMC_MII16_HSSI_TA      0x0001
107 #define LMC_MII16_HSSI_CA      0x0002
108 #define LMC_MII16_HSSI_LA      0x0004
109 #define LMC_MII16_HSSI_LB      0x0008
110 #define LMC_MII16_HSSI_LC      0x0010
111 #define LMC_MII16_HSSI_TM      0x0020
112 #define LMC_MII16_HSSI_CRC     0x0040
113 
114 /*
115  * assignments for the MII register 16 (DS3)
116  */
117 #define LMC_MII16_DS3_ZERO	0x0001
118 #define LMC_MII16_DS3_TRLBK	0x0002
119 #define LMC_MII16_DS3_LNLBK	0x0004
120 #define LMC_MII16_DS3_RAIS	0x0008
121 #define LMC_MII16_DS3_TAIS	0x0010
122 #define LMC_MII16_DS3_BIST	0x0020
123 #define LMC_MII16_DS3_DLOS	0x0040
124 #define LMC_MII16_DS3_CRC	0x1000
125 #define LMC_MII16_DS3_SCRAM	0x2000
126 #define LMC_MII16_DS3_SCRAM_LARS 0x4000
127 
128 /* Note: 2 pairs of LEDs where swapped by mistake
129  * in Xilinx code for DS3 & DS1 adapters */
130 #define LMC_DS3_LED0    0x0100          /* bit 08  yellow */
131 #define LMC_DS3_LED1    0x0080          /* bit 07  blue   */
132 #define LMC_DS3_LED2    0x0400          /* bit 10  green  */
133 #define LMC_DS3_LED3    0x0200          /* bit 09  red    */
134 
135 /*
136  * framer register 0 and 7 (7 is latched and reset on read)
137  */
138 #define LMC_FRAMER_REG0_DLOS            0x80    /* digital loss of service */
139 #define LMC_FRAMER_REG0_OOFS            0x40    /* out of frame sync */
140 #define LMC_FRAMER_REG0_AIS             0x20    /* alarm indication signal */
141 #define LMC_FRAMER_REG0_CIS             0x10    /* channel idle */
142 #define LMC_FRAMER_REG0_LOC             0x08    /* loss of clock */
143 
144 /*
145  * Framer register 9 contains the blue alarm signal
146  */
147 #define LMC_FRAMER_REG9_RBLUE          0x02     /* Blue alarm failure */
148 
149 /*
150  * Framer register 0x10 contains xbit error
151  */
152 #define LMC_FRAMER_REG10_XBIT          0x01     /* X bit error alarm failure */
153 
154 /*
155  * And SSI, LMC1000
156  */
157 #define LMC_MII16_SSI_DTR	0x0001	/* DTR output RW */
158 #define LMC_MII16_SSI_DSR	0x0002	/* DSR input RO */
159 #define LMC_MII16_SSI_RTS	0x0004	/* RTS output RW */
160 #define LMC_MII16_SSI_CTS	0x0008	/* CTS input RO */
161 #define LMC_MII16_SSI_DCD	0x0010	/* DCD input RO */
162 #define LMC_MII16_SSI_RI		0x0020	/* RI input RO */
163 #define LMC_MII16_SSI_CRC                0x1000  /* CRC select - RW */
164 
165 /*
166  * bits 0x0080 through 0x0800 are generic, and described
167  * above with LMC_MII16_LED[0123] _LED_ALL, and _FIFO_RESET
168  */
169 #define LMC_MII16_SSI_LL		0x1000	/* LL output RW */
170 #define LMC_MII16_SSI_RL		0x2000	/* RL output RW */
171 #define LMC_MII16_SSI_TM		0x4000	/* TM input RO */
172 #define LMC_MII16_SSI_LOOP	0x8000	/* loopback enable RW */
173 
174 /*
175  * Some of the MII16 bits are mirrored in the MII17 register as well,
176  * but let's keep thing separate for now, and get only the cable from
177  * the MII17.
178  */
179 #define LMC_MII17_SSI_CABLE_MASK	0x0038	/* mask to extract the cable type */
180 #define LMC_MII17_SSI_CABLE_SHIFT 3	/* shift to extract the cable type */
181 
182 /*
183  * And T1, LMC1200
184  */
185 #define LMC_MII16_T1_UNUSED1    0x0003
186 #define LMC_MII16_T1_XOE                0x0004
187 #define LMC_MII16_T1_RST                0x0008  /* T1 chip reset - RW */
188 #define LMC_MII16_T1_Z                  0x0010  /* output impedance T1=1, E1=0 output - RW */
189 #define LMC_MII16_T1_INTR               0x0020  /* interrupt from 8370 - RO */
190 #define LMC_MII16_T1_ONESEC             0x0040  /* one second square wave - ro */
191 
192 #define LMC_MII16_T1_LED0               0x0100
193 #define LMC_MII16_T1_LED1               0x0080
194 #define LMC_MII16_T1_LED2               0x0400
195 #define LMC_MII16_T1_LED3               0x0200
196 #define LMC_MII16_T1_FIFO_RESET 0x0800
197 
198 #define LMC_MII16_T1_CRC                0x1000  /* CRC select - RW */
199 #define LMC_MII16_T1_UNUSED2    0xe000
200 
201 
202 /* 8370 framer registers  */
203 
204 #define T1FRAMER_ALARM1_STATUS  0x47
205 #define T1FRAMER_ALARM2_STATUS  0x48
206 #define T1FRAMER_FERR_LSB               0x50
207 #define T1FRAMER_FERR_MSB               0x51    /* framing bit error counter */
208 #define T1FRAMER_LCV_LSB                0x54
209 #define T1FRAMER_LCV_MSB                0x55    /* line code violation counter */
210 #define T1FRAMER_AERR                   0x5A
211 
212 /* mask for the above AERR register */
213 #define T1FRAMER_LOF_MASK               (0x0f0) /* receive loss of frame */
214 #define T1FRAMER_COFA_MASK              (0x0c0) /* change of frame alignment */
215 #define T1FRAMER_SEF_MASK               (0x03)  /* severely errored frame  */
216 
217 /* 8370 framer register ALM1 (0x47) values
218  * used to determine link status
219  */
220 
221 #define T1F_SIGFRZ      0x01    /* signaling freeze */
222 #define T1F_RLOF        0x02    /* receive loss of frame alignment */
223 #define T1F_RLOS        0x04    /* receive loss of signal */
224 #define T1F_RALOS       0x08    /* receive analog loss of signal or RCKI loss of clock */
225 #define T1F_RAIS        0x10    /* receive alarm indication signal */
226 #define T1F_UNUSED      0x20
227 #define T1F_RYEL        0x40    /* receive yellow alarm */
228 #define T1F_RMYEL       0x80    /* receive multiframe yellow alarm */
229 
230 #define LMC_T1F_WRITE       0
231 #define LMC_T1F_READ        1
232 
233 typedef struct lmc_st1f_control {
234   int command;
235   int address;
236   int value;
237   char __user *data;
238 } lmc_t1f_control;
239 
240 enum lmc_xilinx_c {
241     lmc_xilinx_reset = 1,
242     lmc_xilinx_load_prom = 2,
243     lmc_xilinx_load = 3
244 };
245 
246 struct lmc_xilinx_control {
247     enum lmc_xilinx_c command;
248     int len;
249     char __user *data;
250 };
251 
252 /* ------------------ end T1 defs ------------------- */
253 
254 #define LMC_MII_LedMask                 0x0780
255 #define LMC_MII_LedBitPos               7
256 
257 #endif
258