| /drivers/video/fbdev/riva/ |
| D | nvreg.h | 31 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask) argument
34 #define SetBF(mask,value) ((value) << (0?mask)) argument
35 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
38 | SetBF(mask,value)))
51 #define DEVICE_DEF(device,mask,value) \ argument
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
54 #define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask) argument
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) argument
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| /drivers/mfd/ |
| D | sec-irq.c | 30 .mask = S2MPS11_IRQ_PWRONF_MASK,
34 .mask = S2MPS11_IRQ_PWRONR_MASK,
38 .mask = S2MPS11_IRQ_JIGONBF_MASK,
42 .mask = S2MPS11_IRQ_JIGONBR_MASK,
46 .mask = S2MPS11_IRQ_ACOKBF_MASK,
50 .mask = S2MPS11_IRQ_ACOKBR_MASK,
54 .mask = S2MPS11_IRQ_PWRON1S_MASK,
58 .mask = S2MPS11_IRQ_MRB_MASK,
62 .mask = S2MPS11_IRQ_RTC60S_MASK,
66 .mask = S2MPS11_IRQ_RTCA1_MASK,
[all …]
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| D | wm8350-irq.c | 42 int mask; member
50 .mask = WM8350_OC_LS_EINT,
56 .mask = WM8350_UV_DC1_EINT,
61 .mask = WM8350_UV_DC2_EINT,
66 .mask = WM8350_UV_DC3_EINT,
71 .mask = WM8350_UV_DC4_EINT,
76 .mask = WM8350_UV_DC5_EINT,
81 .mask = WM8350_UV_DC6_EINT,
86 .mask = WM8350_UV_LDO1_EINT,
91 .mask = WM8350_UV_LDO2_EINT,
[all …]
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| D | da9063-irq.c | 33 .mask = DA9063_M_ONKEY,
37 .mask = DA9063_M_ALARM,
41 .mask = DA9063_M_TICK,
45 .mask = DA9063_M_ADC_RDY,
49 .mask = DA9063_M_SEQ_RDY,
54 .mask = DA9063_M_WAKE,
58 .mask = DA9063_M_TEMP,
62 .mask = DA9063_M_COMP_1V2,
66 .mask = DA9063_M_LDO_LIM,
70 .mask = DA9063_M_UVOV,
[all …]
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| D | wm831x-irq.c | 33 int mask; member
40 .mask = WM831X_TEMP_THW_EINT,
45 .mask = WM831X_GP1_EINT,
50 .mask = WM831X_GP2_EINT,
55 .mask = WM831X_GP3_EINT,
60 .mask = WM831X_GP4_EINT,
65 .mask = WM831X_GP5_EINT,
70 .mask = WM831X_GP6_EINT,
75 .mask = WM831X_GP7_EINT,
80 .mask = WM831X_GP8_EINT,
[all …]
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| D | da9052-irq.c | 41 .mask = DA9052_IRQ_MASK_POS_1,
45 .mask = DA9052_IRQ_MASK_POS_2,
49 .mask = DA9052_IRQ_MASK_POS_3,
53 .mask = DA9052_IRQ_MASK_POS_4,
57 .mask = DA9052_IRQ_MASK_POS_5,
61 .mask = DA9052_IRQ_MASK_POS_6,
65 .mask = DA9052_IRQ_MASK_POS_7,
69 .mask = DA9052_IRQ_MASK_POS_8,
73 .mask = DA9052_IRQ_MASK_POS_1,
77 .mask = DA9052_IRQ_MASK_POS_2,
[all …]
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| D | wm5110-tables.c | 288 .mask = ARIZONA_MICD_CLAMP_FALL_EINT1
291 .mask = ARIZONA_MICD_CLAMP_RISE_EINT1
293 [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 },
294 [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 },
295 [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 },
296 [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 },
313 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
314 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
315 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
316 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
[all …]
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| D | palmas.c | 52 .mask = TPS65917_RESERVED,
55 .mask = TPS65917_INT1_STATUS_PWRON,
58 .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
61 .mask = TPS65917_RESERVED,
64 .mask = TPS65917_INT1_STATUS_PWRDOWN,
67 .mask = TPS65917_INT1_STATUS_HOTDIE,
70 .mask = TPS65917_INT1_STATUS_VSYS_MON,
73 .mask = TPS65917_RESERVED,
77 .mask = TPS65917_RESERVED,
81 .mask = TPS65917_INT2_STATUS_OTP_ERROR,
[all …]
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| D | wm8994-irq.c | 34 .mask = WM8994_TEMP_SHUT_EINT,
38 .mask = WM8994_MIC1_DET_EINT,
42 .mask = WM8994_MIC1_SHRT_EINT,
46 .mask = WM8994_MIC2_DET_EINT,
50 .mask = WM8994_MIC2_SHRT_EINT,
54 .mask = WM8994_FLL1_LOCK_EINT,
58 .mask = WM8994_FLL2_LOCK_EINT,
62 .mask = WM8994_SRC1_LOCK_EINT,
66 .mask = WM8994_SRC2_LOCK_EINT,
70 .mask = WM8994_AIF1DRC1_SIG_DET,
[all …]
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| D | as3722.c | 85 .mask = AS3722_INTERRUPT_MASK1_LID,
88 .mask = AS3722_INTERRUPT_MASK1_ACOK,
91 .mask = AS3722_INTERRUPT_MASK1_ENABLE1,
94 .mask = AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0,
97 .mask = AS3722_INTERRUPT_MASK1_ONKEY_LONG,
100 .mask = AS3722_INTERRUPT_MASK1_ONKEY,
103 .mask = AS3722_INTERRUPT_MASK1_OVTMP,
106 .mask = AS3722_INTERRUPT_MASK1_LOWBAT,
111 .mask = AS3722_INTERRUPT_MASK2_SD0_LV,
115 .mask = AS3722_INTERRUPT_MASK2_SD1_LV,
[all …]
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| D | tps65910.c | 60 .mask = INT_MSK_PWRHOLD_F_IT_MSK_MASK,
64 .mask = INT_MSK_VMBHI_IT_MSK_MASK,
68 .mask = INT_MSK_PWRON_IT_MSK_MASK,
72 .mask = INT_MSK_PWRON_LP_IT_MSK_MASK,
76 .mask = INT_MSK_PWRHOLD_R_IT_MSK_MASK,
80 .mask = INT_MSK_HOTDIE_IT_MSK_MASK,
84 .mask = INT_MSK_RTC_ALARM_IT_MSK_MASK,
88 .mask = INT_MSK_RTC_PERIOD_IT_MSK_MASK,
94 .mask = INT_MSK2_GPIO0_R_IT_MSK_MASK,
98 .mask = INT_MSK2_GPIO0_F_IT_MSK_MASK,
[all …]
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| /drivers/net/ethernet/chelsio/cxgb4/ |
| D | cxgb4_tc_u32_parse.h | 41 int (*val)(struct ch_filter_specification *f, u32 val, u32 mask);
46 u32 val, u32 mask) in cxgb4_fill_ipv4_tos() argument
49 f->mask.tos = (ntohl(mask) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_tos()
55 u32 val, u32 mask) in cxgb4_fill_ipv4_frag() argument
61 mask_val = ntohl(mask) & 0x0000FFFF; in cxgb4_fill_ipv4_frag()
65 f->mask.frag = 1; in cxgb4_fill_ipv4_frag()
68 f->mask.frag = 1; in cxgb4_fill_ipv4_frag()
77 u32 val, u32 mask) in cxgb4_fill_ipv4_proto() argument
80 f->mask.proto = (ntohl(mask) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_proto()
86 u32 val, u32 mask) in cxgb4_fill_ipv4_src_ip() argument
[all …]
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| D | cxgb4_filter.c | 41 static inline bool is_field_set(u32 val, u32 mask) in is_field_set() argument
43 return val || mask; in is_field_set()
46 static inline bool unsupported(u32 conf, u32 conf_mask, u32 val, u32 mask) in unsupported() argument
48 return !(conf & conf_mask) && is_field_set(val, mask); in unsupported()
62 if (unsupported(fconf, FCOE_F, fs->val.fcoe, fs->mask.fcoe) || in validate_filter()
63 unsupported(fconf, PORT_F, fs->val.iport, fs->mask.iport) || in validate_filter()
64 unsupported(fconf, TOS_F, fs->val.tos, fs->mask.tos) || in validate_filter()
66 fs->mask.ethtype) || in validate_filter()
67 unsupported(fconf, MACMATCH_F, fs->val.macidx, fs->mask.macidx) || in validate_filter()
69 fs->mask.matchtype) || in validate_filter()
[all …]
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| /drivers/memory/tegra/ |
| D | tegra114.c | 32 .mask = 0xff,
46 .mask = 0xff,
60 .mask = 0xff,
74 .mask = 0xff,
88 .mask = 0xff,
102 .mask = 0xff,
116 .mask = 0xff,
130 .mask = 0xff,
144 .mask = 0xff,
158 .mask = 0xff,
[all …]
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| D | tegra30.c | 32 .mask = 0xff,
46 .mask = 0xff,
60 .mask = 0xff,
74 .mask = 0xff,
88 .mask = 0xff,
102 .mask = 0xff,
116 .mask = 0xff,
130 .mask = 0xff,
144 .mask = 0xff,
158 .mask = 0xff,
[all …]
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| D | tegra210.c | 34 .mask = 0xff,
48 .mask = 0xff,
62 .mask = 0xff,
76 .mask = 0xff,
90 .mask = 0xff,
104 .mask = 0xff,
118 .mask = 0xff,
132 .mask = 0xff,
146 .mask = 0xff,
160 .mask = 0xff,
[all …]
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| D | tegra124.c | 74 .mask = 0xff,
88 .mask = 0xff,
102 .mask = 0xff,
116 .mask = 0xff,
130 .mask = 0xff,
144 .mask = 0xff,
158 .mask = 0xff,
172 .mask = 0xff,
186 .mask = 0xff,
200 .mask = 0xff,
[all …]
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| /drivers/gpio/ |
| D | gpio-vr41xx.c | 235 u16 mask; in vr41xx_set_irq_trigger() local
238 mask = 1 << pin; in vr41xx_set_irq_trigger()
240 giu_set(GIUINTTYPL, mask); in vr41xx_set_irq_trigger()
242 giu_set(GIUINTHTSELL, mask); in vr41xx_set_irq_trigger()
244 giu_clear(GIUINTHTSELL, mask); in vr41xx_set_irq_trigger()
248 giu_set(GIUFEDGEINHL, mask); in vr41xx_set_irq_trigger()
249 giu_clear(GIUREDGEINHL, mask); in vr41xx_set_irq_trigger()
252 giu_clear(GIUFEDGEINHL, mask); in vr41xx_set_irq_trigger()
253 giu_set(GIUREDGEINHL, mask); in vr41xx_set_irq_trigger()
256 giu_set(GIUFEDGEINHL, mask); in vr41xx_set_irq_trigger()
[all …]
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| /drivers/video/fbdev/ |
| D | c2p_core.h | 21 unsigned int shift, u32 mask) in _transp() argument
23 u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; in _transp()
62 u32 mask = get_mask(n); in transp8() local
67 _transp(d, 0, 1, n, mask); in transp8()
69 _transp(d, 2, 3, n, mask); in transp8()
71 _transp(d, 4, 5, n, mask); in transp8()
73 _transp(d, 6, 7, n, mask); in transp8()
78 _transp(d, 0, 2, n, mask); in transp8()
79 _transp(d, 1, 3, n, mask); in transp8()
81 _transp(d, 4, 6, n, mask); in transp8()
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| /drivers/media/pci/ivtv/ |
| D | ivtv-gpio.c | 161 u16 mask, data; in subdev_s_clock_freq() local
163 mask = itv->card->gpio_audio_freq.mask; in subdev_s_clock_freq()
176 if (mask) in subdev_s_clock_freq()
177 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_clock_freq()
184 u16 mask; in subdev_g_tuner() local
186 mask = itv->card->gpio_audio_detect.mask; in subdev_g_tuner()
187 if (mask == 0 || (read_reg(IVTV_REG_GPIO_IN) & mask)) in subdev_g_tuner()
198 u16 mask, data; in subdev_s_tuner() local
200 mask = itv->card->gpio_audio_mode.mask; in subdev_s_tuner()
217 if (mask) in subdev_s_tuner()
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| /drivers/pinctrl/spear/ |
| D | pinctrl-spear320.c | 37 .mask = 0x00000007,
45 .mask = 0x00000007,
53 .mask = 0x00000007,
61 .mask = 0x00000007,
69 .mask = 0x00000001,
466 .mask = PMX_PL_69_MASK,
470 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
478 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
484 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
523 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
[all …]
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| D | pinctrl-spear1340.c | 220 .mask = PADS_AS_GPIO_REG0_MASK,
224 .mask = PADS_AS_GPIO_REGS_MASK,
228 .mask = PADS_AS_GPIO_REGS_MASK,
232 .mask = PADS_AS_GPIO_REGS_MASK,
236 .mask = PADS_AS_GPIO_REGS_MASK,
240 .mask = PADS_AS_GPIO_REGS_MASK,
244 .mask = PADS_AS_GPIO_REGS_MASK,
248 .mask = PADS_AS_GPIO_REG7_MASK,
281 .mask = FSMC_8BIT_REG7_MASK,
306 .mask = KBD_ROW_COL_MASK,
[all …]
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| /drivers/input/joystick/ |
| D | analog.c | 115 int mask; member
124 unsigned char mask; member
207 if (analog->mask & ANALOG_HAT_FCS) in analog_decode()
215 if (analog->mask & (0x10 << i)) in analog_decode()
218 if (analog->mask & ANALOG_HBTN_CHF) in analog_decode()
222 if (analog->mask & ANALOG_BTN_TL) in analog_decode()
224 if (analog->mask & ANALOG_BTN_TR) in analog_decode()
226 if (analog->mask & ANALOG_BTN_TL2) in analog_decode()
228 if (analog->mask & ANALOG_BTN_TR2) in analog_decode()
232 if (analog->mask & (1 << i)) in analog_decode()
[all …]
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| /drivers/infiniband/sw/rxe/ |
| D | rxe_opcode.c | 44 .mask = {
51 .mask = {
58 .mask = {
68 .mask = {
78 .mask = {
84 .mask = {
90 .mask = {
96 .mask = {
102 .mask = {
110 .mask = {
[all …]
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| /drivers/video/fbdev/core/ |
| D | fb_draw.h | 14 comp(unsigned long a, unsigned long b, unsigned long mask) in comp() argument
16 return ((a ^ b) & mask) ^ b; in comp()
103 u32 mask; in fb_shifted_pixels_mask_u32() local
106 mask = FB_SHIFT_HIGH(p, ~(u32)0, index); in fb_shifted_pixels_mask_u32()
108 mask = 0xff << FB_LEFT_POS(p, 8); in fb_shifted_pixels_mask_u32()
109 mask = FB_SHIFT_LOW(p, mask, index & (bswapmask)) & mask; in fb_shifted_pixels_mask_u32()
110 mask = FB_SHIFT_HIGH(p, mask, index & ~(bswapmask)); in fb_shifted_pixels_mask_u32()
115 mask |= FB_SHIFT_HIGH(p, ~(u32)0, in fb_shifted_pixels_mask_u32()
118 return mask; in fb_shifted_pixels_mask_u32()
125 unsigned long mask; in fb_shifted_pixels_mask_long() local
[all …]
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