| /drivers/gpu/drm/msm/mdp/mdp5/ |
| D | mdp5_kms.c | 31 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); in mdp5_hw_init() local
32 struct platform_device *pdev = mdp5_kms->pdev; in mdp5_hw_init()
36 mdp5_enable(mdp5_kms); in mdp5_hw_init()
62 spin_lock_irqsave(&mdp5_kms->resource_lock, flags); in mdp5_hw_init()
63 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); in mdp5_hw_init()
64 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); in mdp5_hw_init()
66 mdp5_ctlm_hw_reset(mdp5_kms->ctlm); in mdp5_hw_init()
68 mdp5_disable(mdp5_kms); in mdp5_hw_init()
76 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); in mdp5_prepare_commit() local
77 mdp5_enable(mdp5_kms); in mdp5_prepare_commit()
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| D | mdp5_irq.c | 38 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); in mdp5_irq_preinstall() local
39 mdp5_enable(mdp5_kms); in mdp5_irq_preinstall()
40 mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff); in mdp5_irq_preinstall()
41 mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); in mdp5_irq_preinstall()
42 mdp5_disable(mdp5_kms); in mdp5_irq_preinstall()
48 struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms); in mdp5_irq_postinstall() local
49 struct mdp_irq *error_handler = &mdp5_kms->error_handler; in mdp5_irq_postinstall()
57 mdp5_enable(mdp5_kms); in mdp5_irq_postinstall()
59 mdp5_disable(mdp5_kms); in mdp5_irq_postinstall()
66 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); in mdp5_irq_uninstall() local
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| D | mdp5_encoder.c | 35 static struct mdp5_kms *get_kms(struct drm_encoder *encoder) in get_kms()
120 struct mdp5_kms *mdp5_kms = get_kms(encoder); in mdp5_encoder_mode_set() local
196 mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf), in mdp5_encoder_mode_set()
199 mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period); in mdp5_encoder_mode_set()
200 mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len); in mdp5_encoder_mode_set()
201 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf), in mdp5_encoder_mode_set()
204 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start); in mdp5_encoder_mode_set()
205 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end); in mdp5_encoder_mode_set()
206 mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0); in mdp5_encoder_mode_set()
207 mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff); in mdp5_encoder_mode_set()
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| D | mdp5_plane.c | 48 static struct mdp5_kms *get_kms(struct drm_plane *plane) in get_kms()
257 struct mdp5_kms *mdp5_kms = get_kms(plane); in mdp5_plane_prepare_fb() local
264 return msm_framebuffer_prepare(fb, mdp5_kms->id); in mdp5_plane_prepare_fb()
271 struct mdp5_kms *mdp5_kms = get_kms(plane); in mdp5_plane_cleanup_fb() local
278 msm_framebuffer_cleanup(fb, mdp5_kms->id); in mdp5_plane_cleanup_fb()
389 struct mdp5_kms *mdp5_kms = get_kms(plane); in set_scanout_locked() local
392 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe), in set_scanout_locked()
396 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe), in set_scanout_locked()
400 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), in set_scanout_locked()
401 msm_framebuffer_iova(fb, mdp5_kms->id, 0)); in set_scanout_locked()
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| D | mdp5_cmd_encoder.c | 29 static struct mdp5_kms *get_kms(struct drm_encoder *encoder) in get_kms()
101 struct mdp5_kms *mdp5_kms = get_kms(encoder); in pingpong_tearcheck_setup() local
107 if (IS_ERR_OR_NULL(mdp5_kms->vsync_clk)) { in pingpong_tearcheck_setup()
119 vsync_clk_speed = clk_round_rate(mdp5_kms->vsync_clk, VSYNC_CLK_RATE); in pingpong_tearcheck_setup()
131 mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_CONFIG_VSYNC(pp_id), cfg); in pingpong_tearcheck_setup()
132 mdp5_write(mdp5_kms, in pingpong_tearcheck_setup()
134 mdp5_write(mdp5_kms, in pingpong_tearcheck_setup()
136 mdp5_write(mdp5_kms, REG_MDP5_PP_RD_PTR_IRQ(pp_id), mode->vdisplay + 1); in pingpong_tearcheck_setup()
137 mdp5_write(mdp5_kms, REG_MDP5_PP_START_POS(pp_id), mode->vdisplay); in pingpong_tearcheck_setup()
138 mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_THRESH(pp_id), in pingpong_tearcheck_setup()
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| D | mdp5_kms.h | 29 struct mdp5_kms { struct
66 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base) argument
107 static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data) in mdp5_write() argument
109 msm_writel(data, mdp5_kms->mmio + reg); in mdp5_write()
112 static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg) in mdp5_read() argument
114 return msm_readl(mdp5_kms->mmio + reg); in mdp5_read()
184 int mdp5_disable(struct mdp5_kms *mdp5_kms);
185 int mdp5_enable(struct mdp5_kms *mdp5_kms);
195 int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms);
196 void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);
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| D | mdp5_crtc.c | 81 static struct mdp5_kms *get_kms(struct drm_crtc *crtc) in get_kms()
172 struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base); in unref_cursor_worker() local
174 msm_gem_put_iova(val, mdp5_kms->id); in unref_cursor_worker()
198 struct mdp5_kms *mdp5_kms = get_kms(crtc); in blend_setup() local
210 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); in blend_setup()
271 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm, in blend_setup()
273 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm, in blend_setup()
275 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm, in blend_setup()
288 struct mdp5_kms *mdp5_kms = get_kms(crtc); in mdp5_crtc_mode_set_nofb() local
307 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(mdp5_crtc->lm), in mdp5_crtc_mode_set_nofb()
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| D | mdp5_smp.c | 108 struct mdp5_kms *get_kms(struct mdp5_smp *smp) in get_kms()
141 struct mdp5_kms *mdp5_kms = get_kms(smp); in smp_request_block() local
158 dev_err(mdp5_kms->dev->dev, "out of blks (req=%d > avail=%d)\n", in smp_request_block()
194 struct mdp5_kms *mdp5_kms = get_kms(smp); in set_fifo_thresholds() local
201 mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(pipe), val * 1); in set_fifo_thresholds()
202 mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(pipe), val * 2); in set_fifo_thresholds()
203 mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(pipe), val * 3); in set_fifo_thresholds()
215 struct mdp5_kms *mdp5_kms = get_kms(smp); in mdp5_smp_request() local
216 struct drm_device *dev = mdp5_kms->dev; in mdp5_smp_request()
217 int rev = mdp5_cfg_get_hw_rev(mdp5_kms->cfg); in mdp5_smp_request()
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| D | mdp5_ctl.c | 89 struct mdp5_kms *get_kms(struct mdp5_ctl_manager *ctl_mgr) in get_kms()
99 struct mdp5_kms *mdp5_kms = get_kms(ctl->ctlm); in ctl_write() local
102 mdp5_write(mdp5_kms, reg, data); in ctl_write()
108 struct mdp5_kms *mdp5_kms = get_kms(ctl->ctlm); in ctl_read() local
111 return mdp5_read(mdp5_kms, reg); in ctl_read()
114 static void set_display_intf(struct mdp5_kms *mdp5_kms, in set_display_intf() argument
120 spin_lock_irqsave(&mdp5_kms->resource_lock, flags); in set_display_intf()
121 intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL); in set_display_intf()
145 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel); in set_display_intf()
146 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); in set_display_intf()
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| D | mdp5_cfg.h | 109 struct mdp5_kms;
120 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
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| D | mdp5_cfg.c | 494 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms, in mdp5_cfg_init() argument
497 struct drm_device *dev = mdp5_kms->dev; in mdp5_cfg_init()
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| D | mdp5_smp.h | 30 struct mdp5_kms;
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| /drivers/gpu/drm/msm/ |
| D | Makefile | 39 mdp/mdp5/mdp5_kms.o \
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