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Searched refs:mmio (Results 1 – 25 of 245) sorted by relevance

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/drivers/video/fbdev/i810/
Di810_main.c167 static void i810_screen_off(u8 __iomem *mmio, u8 mode) in i810_screen_off() argument
172 i810_writeb(SR_INDEX, mmio, SR01); in i810_screen_off()
173 val = i810_readb(SR_DATA, mmio); in i810_screen_off()
177 while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--); in i810_screen_off()
178 i810_writeb(SR_INDEX, mmio, SR01); in i810_screen_off()
179 i810_writeb(SR_DATA, mmio, val); in i810_screen_off()
191 static void i810_dram_off(u8 __iomem *mmio, u8 mode) in i810_dram_off() argument
195 val = i810_readb(DRAMCH, mmio); in i810_dram_off()
198 i810_writeb(DRAMCH, mmio, val); in i810_dram_off()
210 static void i810_protect_regs(u8 __iomem *mmio, int mode) in i810_protect_regs() argument
[all …]
Di810_accel.c36 static inline void i810_report_error(u8 __iomem *mmio) in i810_report_error() argument
43 i810_readw(IIR, mmio), in i810_report_error()
44 i810_readb(EIR, mmio), in i810_report_error()
45 i810_readl(PGTBL_ER, mmio), in i810_report_error()
46 i810_readl(IPEIR, mmio), in i810_report_error()
47 i810_readl(IPEHR, mmio)); in i810_report_error()
63 u8 __iomem *mmio = par->mmio_start_virtual; in wait_for_space() local
67 head = i810_readl(IRING + 4, mmio) & RBUFFER_HEAD_MASK; in wait_for_space()
76 i810_report_error(mmio); in wait_for_space()
93 u8 __iomem *mmio = par->mmio_start_virtual; in wait_for_engine_idle() local
[all …]
Di810-i2c.c46 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_setscl() local
49 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
51 i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
52 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setscl()
59 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_setsda() local
62 i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
64 i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
65 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setsda()
72 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_getscl() local
74 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK); in i810i2c_getscl()
[all …]
/drivers/net/ethernet/amd/
Damd8111e.c115 void __iomem *mmio = lp->mmio; in amd8111e_read_phy() local
119 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
121 reg_val = readl( mmio + PHY_ACCESS ); in amd8111e_read_phy()
124 ((reg & 0x1f) << 16), mmio +PHY_ACCESS); in amd8111e_read_phy()
126 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
145 void __iomem *mmio = lp->mmio; in amd8111e_write_phy() local
148 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
150 reg_val = readl( mmio + PHY_ACCESS ); in amd8111e_write_phy()
153 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS); in amd8111e_write_phy()
156 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
[all …]
/drivers/staging/comedi/drivers/
Dni_pcidio.c313 dev->mmio + DMA_Line_Control_Group1); in ni_pcidio_request_di_mite_channel()
330 dev->mmio + DMA_Line_Control_Group1); in ni_pcidio_release_di_mite_channel()
397 status = readb(dev->mmio + Interrupt_And_Window_Status); in nidio_interrupt()
398 flags = readb(dev->mmio + Group_1_Flags); in nidio_interrupt()
412 dev->mmio + Master_DMA_And_Interrupt_Control); in nidio_interrupt()
424 writeb(0x00, dev->mmio + in nidio_interrupt()
429 auxdata = readl(dev->mmio + Group_1_FIFO); in nidio_interrupt()
431 flags = readb(dev->mmio + Group_1_Flags); in nidio_interrupt()
436 writeb(ClearExpired, dev->mmio + Group_1_Second_Clear); in nidio_interrupt()
439 writeb(0x00, dev->mmio + OpMode); in nidio_interrupt()
[all …]
Drtd520.c474 writel(0, dev->mmio + LAS0_CGT_CLEAR); in rtd_load_channelgain_list()
475 writel(1, dev->mmio + LAS0_CGT_ENABLE); in rtd_load_channelgain_list()
478 dev->mmio + LAS0_CGT_WRITE); in rtd_load_channelgain_list()
481 writel(0, dev->mmio + LAS0_CGT_ENABLE); in rtd_load_channelgain_list()
483 dev->mmio + LAS0_CGL_WRITE); in rtd_load_channelgain_list()
498 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd520_probe_fifo_depth()
501 writel(0, dev->mmio + LAS0_ADC_CONVERSION); in rtd520_probe_fifo_depth()
506 writew(0, dev->mmio + LAS0_ADC); in rtd520_probe_fifo_depth()
508 fifo_status = readl(dev->mmio + LAS0_ADC); in rtd520_probe_fifo_depth()
518 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd520_probe_fifo_depth()
[all …]
Dni_6527.c99 writeb(val & 0xff, dev->mmio + NI6527_FILT_INTERVAL_REG(0)); in ni6527_set_filter_interval()
101 dev->mmio + NI6527_FILT_INTERVAL_REG(1)); in ni6527_set_filter_interval()
103 dev->mmio + NI6527_FILT_INTERVAL_REG(2)); in ni6527_set_filter_interval()
105 writeb(NI6527_CLR_INTERVAL, dev->mmio + NI6527_CLR_REG); in ni6527_set_filter_interval()
114 writeb(val & 0xff, dev->mmio + NI6527_FILT_ENA_REG(0)); in ni6527_set_filter_enable()
115 writeb((val >> 8) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(1)); in ni6527_set_filter_enable()
116 writeb((val >> 16) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(2)); in ni6527_set_filter_enable()
160 val = readb(dev->mmio + NI6527_DI_REG(0)); in ni6527_di_insn_bits()
161 val |= (readb(dev->mmio + NI6527_DI_REG(1)) << 8); in ni6527_di_insn_bits()
162 val |= (readb(dev->mmio + NI6527_DI_REG(2)) << 16); in ni6527_di_insn_bits()
[all …]
Ddt3000.c241 writew(cmd, dev->mmio + DPR_CMD_MBX); in dt3k_send_cmd()
244 status = readw(dev->mmio + DPR_CMD_MBX); in dt3k_send_cmd()
260 writew(subsys, dev->mmio + DPR_SUBSYS); in dt3k_readsingle()
262 writew(chan, dev->mmio + DPR_PARAMS(0)); in dt3k_readsingle()
263 writew(gain, dev->mmio + DPR_PARAMS(1)); in dt3k_readsingle()
267 return readw(dev->mmio + DPR_PARAMS(2)); in dt3k_readsingle()
273 writew(subsys, dev->mmio + DPR_SUBSYS); in dt3k_writesingle()
275 writew(chan, dev->mmio + DPR_PARAMS(0)); in dt3k_writesingle()
276 writew(0, dev->mmio + DPR_PARAMS(1)); in dt3k_writesingle()
277 writew(data, dev->mmio + DPR_PARAMS(2)); in dt3k_writesingle()
[all …]
Dme_daq.c186 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_dio_insn_config()
196 void __iomem *mmio_porta = dev->mmio + ME_DIO_PORT_A_REG; in me_dio_insn_bits()
197 void __iomem *mmio_portb = dev->mmio + ME_DIO_PORT_B_REG; in me_dio_insn_bits()
231 status = readw(dev->mmio + ME_STATUS_REG); in me_ai_eoc()
261 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ai_insn_read()
263 writew(0x00, dev->mmio + ME_STATUS_REG); /* clear interrupts */ in me_ai_insn_read()
267 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ai_insn_read()
275 writew(val, dev->mmio + ME_AI_FIFO_REG); in me_ai_insn_read()
279 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
283 readw(dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
[all …]
Ddaqboard2000.c271 writew(entry & 0x00ff, dev->mmio + DB2K_REG_ACQ_SCAN_LIST_FIFO); in daqboard2000_write_acq_scan_list_entry()
273 dev->mmio + DB2K_REG_ACQ_SCAN_LIST_FIFO); in daqboard2000_write_acq_scan_list_entry()
324 status = readw(dev->mmio + DB2K_REG_ACQ_STATUS); in daqboard2000_ai_status()
342 dev->mmio + DB2K_REG_ACQ_CONTROL); in daqboard2000_ai_insn_read()
349 writel(1000000, dev->mmio + DB2K_REG_ACQ_PACER_CLOCK_DIV_LOW); in daqboard2000_ai_insn_read()
350 writew(0, dev->mmio + DB2K_REG_ACQ_PACER_CLOCK_DIV_HIGH); in daqboard2000_ai_insn_read()
365 dev->mmio + DB2K_REG_ACQ_CONTROL); in daqboard2000_ai_insn_read()
373 dev->mmio + DB2K_REG_ACQ_CONTROL); in daqboard2000_ai_insn_read()
386 data[i] = readw(dev->mmio + DB2K_REG_ACQ_RESULTS_FIFO); in daqboard2000_ai_insn_read()
388 dev->mmio + DB2K_REG_ACQ_CONTROL); in daqboard2000_ai_insn_read()
[all …]
Dicp_multi.c104 status = readw(dev->mmio + ICP_MULTI_ADC_CSR); in icp_multi_ai_eoc()
130 writew(adc_csr, dev->mmio + ICP_MULTI_ADC_CSR); in icp_multi_ai_insn_read()
135 dev->mmio + ICP_MULTI_ADC_CSR); in icp_multi_ai_insn_read()
144 data[n] = (readw(dev->mmio + ICP_MULTI_AI) >> 4) & 0x0fff; in icp_multi_ai_insn_read()
157 status = readw(dev->mmio + ICP_MULTI_DAC_CSR); in icp_multi_ao_ready()
176 writew(dac_csr, dev->mmio + ICP_MULTI_DAC_CSR); in icp_multi_ao_insn_write()
187 writew(val, dev->mmio + ICP_MULTI_AO); in icp_multi_ao_insn_write()
191 dev->mmio + ICP_MULTI_DAC_CSR); in icp_multi_ao_insn_write()
204 data[1] = readw(dev->mmio + ICP_MULTI_DI); in icp_multi_di_insn_bits()
215 writew(s->state, dev->mmio + ICP_MULTI_DO); in icp_multi_do_insn_bits()
[all …]
Ds626.c113 writel(val, dev->mmio + reg); in s626_mc_enable()
119 writel(cmd << 16, dev->mmio + reg); in s626_mc_disable()
128 val = readl(dev->mmio + reg); in s626_mc_test()
171 if (!(readl(dev->mmio + S626_P_PSR) & S626_PSR_DEBI_S)) in s626_debi_transfer()
185 writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_read()
190 return readl(dev->mmio + S626_P_DEBIAD); in s626_debi_read()
200 writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_write()
201 writel(wdata, dev->mmio + S626_P_DEBIAD); in s626_debi_write()
218 writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_replace()
221 writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_replace()
[all …]
Dni_65xx.c292 writeb(0x00, dev->mmio + NI_65XX_FILTER_ENA(i)); in ni_65xx_disable_input_filters()
295 writel(0x00000000, dev->mmio + NI_65XX_FILTER_REG); in ni_65xx_disable_input_filters()
329 readb(dev->mmio + in ni_65xx_update_edge_detection()
333 readb(dev->mmio + in ni_65xx_update_edge_detection()
338 dev->mmio + NI_65XX_RISE_EDGE_ENA_REG(port)); in ni_65xx_update_edge_detection()
340 dev->mmio + NI_65XX_FALL_EDGE_ENA_REG(port)); in ni_65xx_update_edge_detection()
384 val = readb(dev->mmio + NI_65XX_FILTER_ENA(port)); in ni_65xx_dio_insn_config()
386 writel(interval, dev->mmio + NI_65XX_FILTER_REG); in ni_65xx_dio_insn_config()
391 writeb(val, dev->mmio + NI_65XX_FILTER_ENA(port)); in ni_65xx_dio_insn_config()
398 dev->mmio + NI_65XX_IO_SEL_REG(port)); in ni_65xx_dio_insn_config()
[all …]
Dmite.c218 unsigned int fcr_bits = readl(mite->mmio + MITE_FCR(channel)); in mite_fifo_size()
229 return readl(mite->mmio + MITE_DAR(mite_chan->channel)); in mite_device_bytes_transferred()
240 return readl(mite->mmio + MITE_FCR(mite_chan->channel)) & 0xff; in mite_bytes_in_transit()
377 status = readl(mite->mmio + MITE_CHSR(mite_chan->channel)); in mite_get_status()
381 mite->mmio + MITE_CHOR(mite_chan->channel)); in mite_get_status()
405 writel(CHOR_CLRLC, mite->mmio + MITE_CHOR(mite_chan->channel)); in mite_ack_linkc()
442 mite_chan->mite->mmio + MITE_CHOR(mite_chan->channel)); in mite_dma_reset()
462 writel(CHOR_START, mite->mmio + MITE_CHOR(mite_chan->channel)); in mite_dma_arm()
477 writel(CHOR_ABORT, mite->mmio + MITE_CHOR(mite_chan->channel)); in mite_dma_disarm()
520 writel(chcr, mite->mmio + MITE_CHCR(mite_chan->channel)); in mite_prep_dma()
[all …]
/drivers/ata/
Dsata_sx4.c458 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; in pdc20621_dma_prep() local
469 mmio += PDC_CHIP0_OFS; in pdc20621_dma_prep()
507 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_dma_prep()
518 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; in pdc20621_nodata_prep() local
526 mmio += PDC_CHIP0_OFS; in pdc20621_nodata_prep()
542 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_nodata_prep()
569 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; in __pdc20621_push_hdma() local
572 mmio += PDC_CHIP0_OFS; in __pdc20621_push_hdma()
574 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); in __pdc20621_push_hdma()
575 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ in __pdc20621_push_hdma()
[all …]
Dahci_imx.c78 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert) in imx_phy_crbit_assert() argument
85 crval = readl(mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
90 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
94 srval = readl(mmio + IMX_P0PHYSR); in imx_phy_crbit_assert()
103 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio) in imx_phy_reg_addressing() argument
109 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_addressing()
112 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true); in imx_phy_reg_addressing()
117 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false); in imx_phy_reg_addressing()
124 static int imx_phy_reg_write(u16 val, void __iomem *mmio) in imx_phy_reg_write() argument
130 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_write()
[all …]
Dsata_nv.c608 void __iomem *mmio = pp->ctl_block; in nv_adma_register_mode() local
615 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
618 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
625 tmp = readw(mmio + NV_ADMA_CTL); in nv_adma_register_mode()
626 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); in nv_adma_register_mode()
629 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
632 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
646 void __iomem *mmio = pp->ctl_block; in nv_adma_mode() local
655 tmp = readw(mmio + NV_ADMA_CTL); in nv_adma_mode()
656 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); in nv_adma_mode()
[all …]
Dahci_ceva.c106 void __iomem *mmio = hpriv->mmio; in ahci_ceva_setup() local
117 writel(tmp, mmio + AHCI_VEND_PAXIC); in ahci_ceva_setup()
120 tmp = readl(mmio + HOST_CTL); in ahci_ceva_setup()
122 writel(tmp, mmio + HOST_CTL); in ahci_ceva_setup()
127 writel(tmp, mmio + AHCI_VEND_PCFG); in ahci_ceva_setup()
131 writel(tmp, mmio + AHCI_VEND_PPCFG); in ahci_ceva_setup()
135 writel(tmp, mmio + AHCI_VEND_PP2C); in ahci_ceva_setup()
139 writel(tmp, mmio + AHCI_VEND_PP3C); in ahci_ceva_setup()
143 writel(tmp, mmio + AHCI_VEND_PP4C); in ahci_ceva_setup()
147 writel(tmp, mmio + AHCI_VEND_PP5C); in ahci_ceva_setup()
[all …]
Dahci_xgene.c282 void __iomem *mmio = ctx->hpriv->mmio; in xgene_ahci_set_phy_cfg() local
286 mmio, channel); in xgene_ahci_set_phy_cfg()
287 val = readl(mmio + PORTCFG); in xgene_ahci_set_phy_cfg()
289 writel(val, mmio + PORTCFG); in xgene_ahci_set_phy_cfg()
290 readl(mmio + PORTCFG); /* Force a barrier */ in xgene_ahci_set_phy_cfg()
292 writel(0x0001fffe, mmio + PORTPHY1CFG); in xgene_ahci_set_phy_cfg()
293 readl(mmio + PORTPHY1CFG); /* Force a barrier */ in xgene_ahci_set_phy_cfg()
294 writel(0x28183219, mmio + PORTPHY2CFG); in xgene_ahci_set_phy_cfg()
295 readl(mmio + PORTPHY2CFG); /* Force a barrier */ in xgene_ahci_set_phy_cfg()
296 writel(0x13081008, mmio + PORTPHY3CFG); in xgene_ahci_set_phy_cfg()
[all …]
/drivers/phy/
Dphy-qcom-ipq806x-sata.c27 void __iomem *mmio; member
67 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
69 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
71 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) & in qcom_ipq806x_sata_phy_init()
76 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0); in qcom_ipq806x_sata_phy_init()
78 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) & in qcom_ipq806x_sata_phy_init()
85 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1); in qcom_ipq806x_sata_phy_init()
87 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) & in qcom_ipq806x_sata_phy_init()
90 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2); in qcom_ipq806x_sata_phy_init()
93 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
[all …]
/drivers/ntb/hw/amd/
Dntb_hw_amd.c121 void __iomem *mmio, *peer_mmio; in amd_ntb_mw_set_trans() local
135 mmio = ndev->self_mmio; in amd_ntb_mw_set_trans()
156 write64(limit, mmio + limit_reg); in amd_ntb_mw_set_trans()
157 reg_val = read64(mmio + limit_reg); in amd_ntb_mw_set_trans()
159 write64(base_addr, mmio + limit_reg); in amd_ntb_mw_set_trans()
185 writel(limit, mmio + limit_reg); in amd_ntb_mw_set_trans()
186 reg_val = readl(mmio + limit_reg); in amd_ntb_mw_set_trans()
188 writel(base_addr, mmio + limit_reg); in amd_ntb_mw_set_trans()
249 void __iomem *mmio = ndev->self_mmio; in amd_ntb_link_enable() local
254 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_ntb_link_enable()
[all …]
/drivers/ntb/hw/intel/
Dntb_hw_intel.c153 static inline u64 _ioread64(void __iomem *mmio) in _ioread64() argument
157 low = ioread32(mmio); in _ioread64()
158 high = ioread32(mmio + sizeof(u32)); in _ioread64()
169 static inline void _iowrite64(u64 val, void __iomem *mmio) in _iowrite64() argument
171 iowrite32(val, mmio); in _iowrite64()
172 iowrite32(val >> 32, mmio + sizeof(u32)); in _iowrite64()
269 void __iomem *mmio) in ndev_db_read() argument
274 return ndev->reg->db_ioread(mmio); in ndev_db_read()
278 void __iomem *mmio) in ndev_db_write() argument
286 ndev->reg->db_iowrite(db_bits, mmio); in ndev_db_write()
[all …]
/drivers/ssb/
Dscan.c177 lo = readw(bus->mmio + offset); in scan_read32()
178 hi = readw(bus->mmio + offset + 2); in scan_read32()
184 return readl(bus->mmio + offset); in scan_read32()
207 iounmap(bus->mmio); in ssb_iounmap()
211 pci_iounmap(bus->host_pci, bus->mmio); in ssb_iounmap()
219 bus->mmio = NULL; in ssb_iounmap()
226 void __iomem *mmio = NULL; in ssb_ioremap() local
233 mmio = ioremap(baseaddr, SSB_CORE_SIZE); in ssb_ioremap()
237 mmio = pci_iomap(bus->host_pci, 0, ~0UL); in ssb_ioremap()
244 mmio = (void __iomem *)baseaddr; in ssb_ioremap()
[all …]
/drivers/gpu/drm/bochs/
Dbochs_hw.c17 if (bochs->mmio) { in bochs_vga_writeb()
19 writeb(val, bochs->mmio + offset); in bochs_vga_writeb()
29 if (bochs->mmio) { in bochs_dispi_read()
31 ret = readw(bochs->mmio + offset); in bochs_dispi_read()
41 if (bochs->mmio) { in bochs_dispi_write()
43 writew(val, bochs->mmio + offset); in bochs_dispi_write()
65 bochs->mmio = ioremap(ioaddr, iosize); in bochs_hw_init()
66 if (bochs->mmio == NULL) { in bochs_hw_init()
119 if (bochs->mmio && pdev->revision >= 2) { in bochs_hw_init()
120 qext_size = readl(bochs->mmio + 0x600); in bochs_hw_init()
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/drivers/net/ethernet/cavium/liquidio/
Docteon_main.h90 if (oct->mmio[baridx].done) in octeon_unmap_pci_barx()
91 iounmap(oct->mmio[baridx].hw_addr); in octeon_unmap_pci_barx()
93 if (oct->mmio[baridx].start) in octeon_unmap_pci_barx()
114 oct->mmio[baridx].start = pci_resource_start(oct->pci_dev, baridx * 2); in octeon_map_pci_barx()
115 oct->mmio[baridx].len = pci_resource_len(oct->pci_dev, baridx * 2); in octeon_map_pci_barx()
117 mapped_len = oct->mmio[baridx].len; in octeon_map_pci_barx()
124 oct->mmio[baridx].hw_addr = in octeon_map_pci_barx()
125 ioremap(oct->mmio[baridx].start, mapped_len); in octeon_map_pci_barx()
126 oct->mmio[baridx].mapped_len = mapped_len; in octeon_map_pci_barx()
129 baridx, oct->mmio[baridx].start, mapped_len, in octeon_map_pci_barx()
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