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Searched refs:mux_clks (Results 1 – 9 of 9) sorted by relevance

/drivers/clk/samsung/
Dclk-exynos7.c193 .mux_clks = topc_mux_clks,
385 .mux_clks = top0_mux_clks,
562 .mux_clks = top1_mux_clks,
611 .mux_clks = ccore_mux_clks,
678 .mux_clks = peric0_mux_clks,
802 .mux_clks = peric1_mux_clks,
857 .mux_clks = peris_mux_clks,
967 .mux_clks = fsys0_mux_clks,
1096 .mux_clks = fsys1_mux_clks,
1209 .mux_clks = mscl_mux_clks,
[all …]
Dclk-exynos5260.c135 .mux_clks = aud_mux_clks,
325 .mux_clks = disp_mux_clks,
391 .mux_clks = egl_mux_clks,
491 .mux_clks = fsys_mux_clks,
580 .mux_clks = g2d_mux_clks,
643 .mux_clks = g3d_mux_clks,
776 .mux_clks = gscl_mux_clks,
895 .mux_clks = isp_mux_clks,
961 .mux_clks = kfc_mux_clks,
1015 .mux_clks = mfc_mux_clks,
[all …]
Dclk-exynos3250.c240 static const struct samsung_mux_clock mux_clks[] __initconst = { variable
778 .mux_clks = mux_clks,
779 .nr_mux_clks = ARRAY_SIZE(mux_clks),
923 .mux_clks = dmc_mux_clks,
Dclk-exynos5433.c775 .mux_clks = top_mux_clks,
849 .mux_clks = cpif_mux_clks,
1499 .mux_clks = mif_mux_clks,
2288 .mux_clks = fsys_mux_clks,
2412 .mux_clks = g2d_mux_clks,
2829 .mux_clks = disp_mux_clks,
3001 .mux_clks = aud_mux_clks,
3162 .mux_clks = bus2_mux_clks,
3287 .mux_clks = g3d_mux_clks,
3430 .mux_clks = gscl_mux_clks,
[all …]
Dclk.c404 if (cmu->mux_clks) in samsung_cmu_register_one()
405 samsung_clk_register_mux(ctx, cmu->mux_clks, in samsung_cmu_register_one()
Dclk-s5pv210.c415 static const struct samsung_mux_clock mux_clks[] __initconst = { variable
815 samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks)); in __s5pv210_clk_init()
Dclk-exynos5410.c259 .mux_clks = exynos5410_mux_clks,
Dclk-exynos4415.c928 .mux_clks = exynos4415_mux_clks,
1008 .mux_clks = exynos4415_dmc_mux_clks,
Dclk.h336 const struct samsung_mux_clock *mux_clks; member