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Searched refs:nr_cmds (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/msm/
Dmsm_gem_submit.c34 struct msm_gpu *gpu, uint32_t nr_bos, uint32_t nr_cmds) in submit_create() argument
38 ((u64)nr_cmds * sizeof(submit->cmd[0])); in submit_create()
55 submit->nr_cmds = 0; in submit_create()
421 submit = submit_create(dev, gpu, args->nr_bos, args->nr_cmds); in msm_ioctl_gem_submit()
466 for (i = 0; i < args->nr_cmds; i++) { in msm_ioctl_gem_submit()
524 submit->nr_cmds = i; in msm_ioctl_gem_submit()
Dmsm_gem.h110 unsigned int nr_cmds; member
Dmsm_rd.c350 for (i = 0; i < submit->nr_cmds; i++) { in msm_rd_dump_submit()
/drivers/block/
Dcciss.c293 int nr_cmds) in cciss_free_sg_chain_blocks() argument
299 for (i = 0; i < nr_cmds; i++) { in cciss_free_sg_chain_blocks()
307 ctlr_info_t *h, int chainsize, int nr_cmds) in cciss_allocate_sg_chain_blocks() argument
315 cmd_sg_list = kmalloc(sizeof(*cmd_sg_list) * nr_cmds, GFP_KERNEL); in cciss_allocate_sg_chain_blocks()
320 for (j = 0; j < nr_cmds; j++) { in cciss_allocate_sg_chain_blocks()
332 cciss_free_sg_chain_blocks(cmd_sg_list, nr_cmds); in cciss_allocate_sg_chain_blocks()
992 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds); in cmd_alloc()
993 if (i == h->nr_cmds) in cmd_alloc()
1787 if ((find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds)) == h->nr_cmds) in cciss_check_queues()
1809 if ((find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds)) == h->nr_cmds) { in cciss_check_queues()
[all …]
Dcciss.h68 int nr_cmds; /* Number of commands allowed on this controller */ member
432 int nr_cmds; /* Max cmds this kind of ctlr can handle. */ member
/drivers/nvme/target/
Drdma.c310 int nr_cmds, bool admin) in nvmet_rdma_alloc_cmds() argument
315 cmds = kcalloc(nr_cmds, sizeof(struct nvmet_rdma_cmd), GFP_KERNEL); in nvmet_rdma_alloc_cmds()
319 for (i = 0; i < nr_cmds; i++) { in nvmet_rdma_alloc_cmds()
336 struct nvmet_rdma_cmd *cmds, int nr_cmds, bool admin) in nvmet_rdma_free_cmds() argument
340 for (i = 0; i < nr_cmds; i++) in nvmet_rdma_free_cmds()
/drivers/scsi/
Dhpsa.c1680 qdepth = min(h->nr_cmds, qdepth + in hpsa_figure_phys_disk_ptrs()
1705 logical_drive->queue_depth = h->nr_cmds; in hpsa_figure_phys_disk_ptrs()
1757 for (i = 0; i < h->nr_cmds; i++) { in hpsa_find_outstanding_commands_for_dev()
2074 for (i = 0; i < h->nr_cmds; i++) { in hpsa_free_ioaccel2_sg_chain_blocks()
2090 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds, in hpsa_allocate_ioaccel2_sg_chain_blocks()
2094 for (i = 0; i < h->nr_cmds; i++) { in hpsa_allocate_ioaccel2_sg_chain_blocks()
2114 for (i = 0; i < h->nr_cmds; i++) { in hpsa_free_sg_chain_blocks()
2129 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds, in hpsa_alloc_sg_chain_blocks()
2135 for (i = 0; i < h->nr_cmds; i++) { in hpsa_alloc_sg_chain_blocks()
3044 for (i = 0; i < h->nr_cmds; i++) { in hpsa_do_reset()
[all …]
Dhpsa.h168 int nr_cmds; /* Number of commands allowed on this controller */ member
/drivers/gpu/drm/msm/adreno/
Dadreno_gpu.c144 for (i = 0; i < submit->nr_cmds; i++) { in adreno_submit()