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Searched refs:output_rate (Results 1 – 4 of 4) sorted by relevance

/drivers/clk/tegra/
Dclk-divider.c92 unsigned long output_rate = *prate; in clk_frac_div_round_rate() local
95 return output_rate; in clk_frac_div_round_rate()
97 div = get_div(divider, rate, output_rate); in clk_frac_div_round_rate()
103 return DIV_ROUND_UP(output_rate * mul, div + mul); in clk_frac_div_round_rate()
Dclk-pll.c502 sel->output_rate == rate) in _get_table_rate()
517 cfg->output_rate = sel->output_rate; in _get_table_rate()
561 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; in _calc_rate()
562 cfg->output_rate <<= 1) in _calc_rate()
566 cfg->n = cfg->output_rate / cfreq; in _calc_rate()
571 || cfg->output_rate > pll->params->vco_max) { in _calc_rate()
575 cfg->output_rate >>= p_div; in _calc_rate()
838 return cfg.output_rate; in clk_pll_round_rate()
1181 cfg->output_rate = rate * p; in _calc_dynamic_ramp_rate()
1182 cfg->n = cfg->output_rate * cfg->m / parent_rate; in _calc_dynamic_ramp_rate()
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Dclk.h117 unsigned long output_rate; member
Dclk-tegra210.c1232 cfg->output_rate = rate; in tegra210_pll_fixed_mdiv_cfg()