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Searched refs:outpw (Results 1 – 7 of 7) sorted by relevance

/drivers/net/fddi/skfp/
Dfplustm.c160 outpw(FM_A(FM_CMDREG1),FM_IRMEMWO) ;
198 outpw(FM_A(FM_RPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* RPR1 */ in set_recvptr()
199 outpw(FM_A(FM_SWPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* SWPR1 */ in set_recvptr()
200 outpw(FM_A(FM_WPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* WPR1 */ in set_recvptr()
201 outpw(FM_A(FM_EARV1),smc->hw.fp.fifo.tx_s_start-1) ; /* EARV1 */ in set_recvptr()
207 outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rx2_fifo_start) ; in set_recvptr()
208 outpw(FM_A(FM_SWPR2),smc->hw.fp.fifo.rx2_fifo_start) ; in set_recvptr()
209 outpw(FM_A(FM_WPR2),smc->hw.fp.fifo.rx2_fifo_start) ; in set_recvptr()
210 outpw(FM_A(FM_EARV2),smc->hw.fp.fifo.rbc_ram_end-1) ; in set_recvptr()
213 outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rbc_ram_end-1) ; in set_recvptr()
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Dhwt.c82 outpw(ADDR(B2_TI_CRTL), TIM_START) ; /* Start timer. */ in hwt_start()
103 outpw(ADDR(B2_TI_CRTL), TIM_STOP) ; in hwt_stop()
104 outpw(ADDR(B2_TI_CRTL), TIM_CL_IRQ) ; in hwt_stop()
205 outpw(ADDR(B2_TI_CRTL), TIM_STOP) ; in hwt_quick_read()
208 outpw(ADDR(B2_TI_CRTL), TIM_START) ; in hwt_quick_read()
Dpcmplc.c430 outpw(PLC(p,PL_CNTRL_B),0) ; in plc_init()
431 outpw(PLC(p,PL_CNTRL_B),PL_PCM_STOP) ; in plc_init()
432 outpw(PLC(p,PL_CNTRL_A),0) ; in plc_init()
443 outpw(PLC(p,PL_CNTRL_C),PLCS_CONTROL_C_S) ; in plc_init()
445 outpw(PLC(p,PL_T_FOT_ASS),PLCS_FASSERT_S) ; in plc_init()
446 outpw(PLC(p,PL_T_FOT_DEASS),PLCS_FDEASSERT_S) ; in plc_init()
450 outpw(PLC(p,PL_CNTRL_C),PLCS_CONTROL_C_U) ; in plc_init()
452 outpw(PLC(p,PL_T_FOT_ASS),PLCS_FASSERT_U) ; in plc_init()
453 outpw(PLC(p,PL_T_FOT_DEASS),PLCS_FDEASSERT_U) ; in plc_init()
462 outpw(PLC(p,pltm[i].timer),pltm[i].para) ; in plc_init()
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Ddrvfbi.c102 outpw(FM_A(FM_MDREG1),FM_MINIT) ; in card_start()
118 outpw(PCI_C(PCI_STATUS), word | PCI_ERRBITS) ; in card_start()
172 outpw(FM_A(FM_MDREG1),FM_MINIT) ; in card_stop()
556 outpw(ADDR(B2_WDOG_CRTL),TIM_START) ; /* Start timer. */ in smt_start_watchdog()
570 outpw(ADDR(B2_WDOG_CRTL),TIM_STOP) ; /* Stop timer. */ in smt_stop_watchdog()
/drivers/net/fddi/skfp/h/
Dskfbi.h1036 #define CLEAR(io,mask) outpw((io),inpw(io)&(~(mask)))
1037 #define SET(io,mask) outpw((io),inpw(io)|(mask))
1039 #define SETMASK(io,val,mask) outpw((io),(inpw(io) & ~(mask)) | (val))
1050 #define MARW(ma) outpw(FM_A(FM_MARW),(unsigned int)(ma))
1051 #define MARR(ma) outpw(FM_A(FM_MARR),(unsigned int)(ma))
1057 #define MDRW(dd) outpw(FM_A(FM_MDRU),(unsigned int)((dd)>>16)) ;\
1058 outpw(FM_A(FM_MDRL),(unsigned int)(dd))
1084 #define OUT_82c54_TIMER(port,val) outpw(TI_A(port),(val)<<8)
Dtypes.h36 #define outpw(p,s) iowrite16(s,p) macro
/drivers/scsi/
Dadvansys.c84 #define outpw(port, word) outw((word), (port)) macro
826 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
827 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
831 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
833 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
835 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
839 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
844 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
851 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
855 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
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