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Searched refs:par (Results 1 – 25 of 267) sorted by relevance

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/drivers/video/fbdev/nvidia/
Dnv_setup.c60 void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value) in NVWriteCrtc() argument
62 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); in NVWriteCrtc()
63 VGA_WR08(par->PCIO, par->IOBase + 0x05, value); in NVWriteCrtc()
65 u8 NVReadCrtc(struct nvidia_par *par, u8 index) in NVReadCrtc() argument
67 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); in NVReadCrtc()
68 return (VGA_RD08(par->PCIO, par->IOBase + 0x05)); in NVReadCrtc()
70 void NVWriteGr(struct nvidia_par *par, u8 index, u8 value) in NVWriteGr() argument
72 VGA_WR08(par->PVIO, VGA_GFX_I, index); in NVWriteGr()
73 VGA_WR08(par->PVIO, VGA_GFX_D, value); in NVWriteGr()
75 u8 NVReadGr(struct nvidia_par *par, u8 index) in NVReadGr() argument
[all …]
Dnv_hw.c57 void NVLockUnlock(struct nvidia_par *par, int Lock) in NVLockUnlock() argument
61 VGA_WR08(par->PCIO, 0x3D4, 0x1F); in NVLockUnlock()
62 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57); in NVLockUnlock()
64 VGA_WR08(par->PCIO, 0x3D4, 0x11); in NVLockUnlock()
65 cr11 = VGA_RD08(par->PCIO, 0x3D5); in NVLockUnlock()
70 VGA_WR08(par->PCIO, 0x3D5, cr11); in NVLockUnlock()
73 int NVShowHideCursor(struct nvidia_par *par, int ShowHide) in NVShowHideCursor() argument
75 int cur = par->CurrentState->cursor1; in NVShowHideCursor()
77 par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) | in NVShowHideCursor()
79 VGA_WR08(par->PCIO, 0x3D4, 0x31); in NVShowHideCursor()
[all …]
Dnv_accel.c74 struct nvidia_par *par = info->par; in nvidiafb_safe_mode() local
78 par->lockup = 1; in nvidiafb_safe_mode()
83 struct nvidia_par *par = info->par; in NVFlush() local
86 while (--count && READ_GET(par) != par->dmaPut) ; in NVFlush()
96 struct nvidia_par *par = info->par; in NVSync() local
99 while (--count && NV_RD32(par->PGRAPH, 0x0700)) ; in NVSync()
107 static void NVDmaKickoff(struct nvidia_par *par) in NVDmaKickoff() argument
109 if (par->dmaCurrent != par->dmaPut) { in NVDmaKickoff()
110 par->dmaPut = par->dmaCurrent; in NVDmaKickoff()
111 WRITE_PUT(par, par->dmaPut); in NVDmaKickoff()
[all …]
/drivers/video/fbdev/savage/
Dsavagefb_driver.c81 static void vgaHWSeqReset(struct savagefb_par *par, int start) in vgaHWSeqReset() argument
84 VGAwSEQ(0x00, 0x01, par); /* Synchronous Reset */ in vgaHWSeqReset()
86 VGAwSEQ(0x00, 0x03, par); /* End Reset */ in vgaHWSeqReset()
89 static void vgaHWProtect(struct savagefb_par *par, int on) in vgaHWProtect() argument
97 tmp = VGArSEQ(0x01, par); in vgaHWProtect()
99 vgaHWSeqReset(par, 1); /* start synchronous reset */ in vgaHWProtect()
100 VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */ in vgaHWProtect()
102 VGAenablePalette(par); in vgaHWProtect()
108 tmp = VGArSEQ(0x01, par); in vgaHWProtect()
110 VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */ in vgaHWProtect()
[all …]
/drivers/staging/fbtft/
Dfb_ra8875.c26 static int write_spi(struct fbtft_par *par, void *buf, size_t len) in write_spi() argument
35 fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len, in write_spi()
38 if (!par->spi) { in write_spi()
39 dev_err(par->info->device, in write_spi()
45 if (par->txbuf.dma && buf == par->txbuf.buf) { in write_spi()
46 t.tx_dma = par->txbuf.dma; in write_spi()
50 return spi_sync(par->spi, &m); in write_spi()
53 static int init_display(struct fbtft_par *par) in init_display() argument
55 gpio_set_value(par->gpio.dc, 1); in init_display()
57 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, in init_display()
[all …]
Dfb_bd663474.c34 static int init_display(struct fbtft_par *par) in init_display() argument
36 if (par->gpio.cs != -1) in init_display()
37 gpio_set_value(par->gpio.cs, 0); /* Activate chip */ in init_display()
39 par->fbtftops.reset(par); in init_display()
44 write_reg(par, 0x000, 0x0001); /*oscillator 0: stop, 1: operation */ in init_display()
48 write_reg(par, 0x100, 0x0000); /* power supply setup */ in init_display()
49 write_reg(par, 0x101, 0x0000); in init_display()
50 write_reg(par, 0x102, 0x3110); in init_display()
51 write_reg(par, 0x103, 0xe200); in init_display()
52 write_reg(par, 0x110, 0x009d); in init_display()
[all …]
Dfb_ili9320.c32 static unsigned int read_devicecode(struct fbtft_par *par) in read_devicecode() argument
37 write_reg(par, 0x0000); in read_devicecode()
38 ret = par->fbtftops.read(par, rxbuf, 4); in read_devicecode()
42 static int init_display(struct fbtft_par *par) in init_display() argument
46 par->fbtftops.reset(par); in init_display()
48 devcode = read_devicecode(par); in init_display()
49 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "Device code: 0x%04X\n", in init_display()
52 dev_warn(par->info->device, in init_display()
60 write_reg(par, 0x00E5, 0x8000); in init_display()
63 write_reg(par, 0x0000, 0x0001); in init_display()
[all …]
Dfb_upd161704.c34 static int init_display(struct fbtft_par *par) in init_display() argument
36 par->fbtftops.reset(par); in init_display()
38 if (par->gpio.cs != -1) in init_display()
39 gpio_set_value(par->gpio.cs, 0); /* Activate chip */ in init_display()
44 write_reg(par, 0x0003, 0x0001); /* Soft reset */ in init_display()
47 write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */ in init_display()
51 write_reg(par, 0x0024, 0x007B); /* amplitude setting */ in init_display()
53 write_reg(par, 0x0025, 0x003B); /* amplitude setting */ in init_display()
54 write_reg(par, 0x0026, 0x0034); /* amplitude setting */ in init_display()
56 write_reg(par, 0x0027, 0x0004); /* amplitude setting */ in init_display()
[all …]
Dfb_ssd1289.c36 static int init_display(struct fbtft_par *par) in init_display() argument
38 par->fbtftops.reset(par); in init_display()
40 if (par->gpio.cs != -1) in init_display()
41 gpio_set_value(par->gpio.cs, 0); /* Activate chip */ in init_display()
43 write_reg(par, 0x00, 0x0001); in init_display()
44 write_reg(par, 0x03, 0xA8A4); in init_display()
45 write_reg(par, 0x0C, 0x0000); in init_display()
46 write_reg(par, 0x0D, 0x080C); in init_display()
47 write_reg(par, 0x0E, 0x2B00); in init_display()
48 write_reg(par, 0x1E, 0x00B7); in init_display()
[all …]
Dfb_s6d1121.c37 static int init_display(struct fbtft_par *par) in init_display() argument
39 par->fbtftops.reset(par); in init_display()
41 if (par->gpio.cs != -1) in init_display()
42 gpio_set_value(par->gpio.cs, 0); /* Activate chip */ in init_display()
46 write_reg(par, 0x0011, 0x2004); in init_display()
47 write_reg(par, 0x0013, 0xCC00); in init_display()
48 write_reg(par, 0x0015, 0x2600); in init_display()
49 write_reg(par, 0x0014, 0x252A); in init_display()
50 write_reg(par, 0x0012, 0x0033); in init_display()
51 write_reg(par, 0x0013, 0xCC04); in init_display()
[all …]
Dfb_ili9325.c96 static int init_display(struct fbtft_par *par) in init_display() argument
98 par->fbtftops.reset(par); in init_display()
100 if (par->gpio.cs != -1) in init_display()
101 gpio_set_value(par->gpio.cs, 0); /* Activate chip */ in init_display()
112 write_reg(par, 0x00E3, 0x3008); /* Set internal timing */ in init_display()
113 write_reg(par, 0x00E7, 0x0012); /* Set internal timing */ in init_display()
114 write_reg(par, 0x00EF, 0x1231); /* Set internal timing */ in init_display()
115 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ in init_display()
116 write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ in init_display()
117 write_reg(par, 0x0004, 0x0000); /* Resize register */ in init_display()
[all …]
Dfb_ssd1306.c41 static int init_display(struct fbtft_par *par) in init_display() argument
43 par->fbtftops.reset(par); in init_display()
45 if (par->gamma.curves[0] == 0) { in init_display()
46 mutex_lock(&par->gamma.lock); in init_display()
47 if (par->info->var.yres == 64) in init_display()
48 par->gamma.curves[0] = 0xCF; in init_display()
50 par->gamma.curves[0] = 0x8F; in init_display()
51 mutex_unlock(&par->gamma.lock); in init_display()
55 write_reg(par, 0xAE); in init_display()
58 write_reg(par, 0xD5); in init_display()
[all …]
Dfb_ssd1305.c42 static int init_display(struct fbtft_par *par) in init_display() argument
44 par->fbtftops.reset(par); in init_display()
46 if (par->gamma.curves[0] == 0) { in init_display()
47 mutex_lock(&par->gamma.lock); in init_display()
48 if (par->info->var.yres == 64) in init_display()
49 par->gamma.curves[0] = 0xCF; in init_display()
51 par->gamma.curves[0] = 0x8F; in init_display()
52 mutex_unlock(&par->gamma.lock); in init_display()
56 write_reg(par, 0xAE); in init_display()
59 write_reg(par, 0xD5); in init_display()
[all …]
Dfbtft-core.c75 static unsigned long fbtft_request_gpios_match(struct fbtft_par *par, in fbtft_request_gpios_match() argument
81 fbtft_par_dbg(DEBUG_REQUEST_GPIOS_MATCH, par, "%s('%s')\n", in fbtft_request_gpios_match()
85 par->gpio.reset = gpio->gpio; in fbtft_request_gpios_match()
88 par->gpio.dc = gpio->gpio; in fbtft_request_gpios_match()
91 par->gpio.cs = gpio->gpio; in fbtft_request_gpios_match()
94 par->gpio.wr = gpio->gpio; in fbtft_request_gpios_match()
97 par->gpio.rd = gpio->gpio; in fbtft_request_gpios_match()
100 par->gpio.latch = gpio->gpio; in fbtft_request_gpios_match()
105 par->gpio.db[val] = gpio->gpio; in fbtft_request_gpios_match()
109 par->gpio.led[0] = gpio->gpio; in fbtft_request_gpios_match()
[all …]
Dfb_hx8347d.c32 static int init_display(struct fbtft_par *par) in init_display() argument
34 par->fbtftops.reset(par); in init_display()
37 write_reg(par, 0xEA, 0x00); in init_display()
38 write_reg(par, 0xEB, 0x20); in init_display()
39 write_reg(par, 0xEC, 0x0C); in init_display()
40 write_reg(par, 0xED, 0xC4); in init_display()
41 write_reg(par, 0xE8, 0x40); in init_display()
42 write_reg(par, 0xE9, 0x38); in init_display()
43 write_reg(par, 0xF1, 0x01); in init_display()
44 write_reg(par, 0xF2, 0x10); in init_display()
[all …]
/drivers/video/fbdev/
Dbroadsheetfb.c119 static void broadsheet_gpio_issue_data(struct broadsheetfb_par *par, u16 data) in broadsheet_gpio_issue_data() argument
121 par->board->set_ctl(par, BS_WR, 0); in broadsheet_gpio_issue_data()
122 par->board->set_hdb(par, data); in broadsheet_gpio_issue_data()
123 par->board->set_ctl(par, BS_WR, 1); in broadsheet_gpio_issue_data()
126 static void broadsheet_gpio_issue_cmd(struct broadsheetfb_par *par, u16 data) in broadsheet_gpio_issue_cmd() argument
128 par->board->set_ctl(par, BS_DC, 0); in broadsheet_gpio_issue_cmd()
129 broadsheet_gpio_issue_data(par, data); in broadsheet_gpio_issue_cmd()
132 static void broadsheet_gpio_send_command(struct broadsheetfb_par *par, u16 data) in broadsheet_gpio_send_command() argument
134 par->board->wait_for_rdy(par); in broadsheet_gpio_send_command()
136 par->board->set_ctl(par, BS_CS, 0); in broadsheet_gpio_send_command()
[all …]
Dauo_k190x.c57 static void auok190x_issue_data(struct auok190xfb_par *par, u16 data) in auok190x_issue_data() argument
59 par->board->set_ctl(par, AUOK190X_I80_WR, 0); in auok190x_issue_data()
60 par->board->set_hdb(par, data); in auok190x_issue_data()
61 par->board->set_ctl(par, AUOK190X_I80_WR, 1); in auok190x_issue_data()
64 static void auok190x_issue_cmd(struct auok190xfb_par *par, u16 data) in auok190x_issue_cmd() argument
66 par->board->set_ctl(par, AUOK190X_I80_DC, 0); in auok190x_issue_cmd()
67 auok190x_issue_data(par, data); in auok190x_issue_cmd()
68 par->board->set_ctl(par, AUOK190X_I80_DC, 1); in auok190x_issue_cmd()
82 static int auok190x_issue_pixels_rgb565(struct auok190xfb_par *par, int size, in auok190x_issue_pixels_rgb565() argument
85 struct fb_var_screeninfo *var = &par->info->var; in auok190x_issue_pixels_rgb565()
[all …]
Di740fb.c94 static inline void i740outb(struct i740fb_par *par, u16 port, u8 val) in i740outb() argument
96 vga_mm_w(par->regs, port, val); in i740outb()
98 static inline u8 i740inb(struct i740fb_par *par, u16 port) in i740inb() argument
100 return vga_mm_r(par->regs, port); in i740inb()
102 static inline void i740outreg(struct i740fb_par *par, u16 port, u8 reg, u8 val) in i740outreg() argument
104 vga_mm_w_fast(par->regs, port, reg, val); in i740outreg()
106 static inline u8 i740inreg(struct i740fb_par *par, u16 port, u8 reg) in i740inreg() argument
108 vga_mm_w(par->regs, port, reg); in i740inreg()
109 return vga_mm_r(par->regs, port+1); in i740inreg()
111 static inline void i740outreg_mask(struct i740fb_par *par, u16 port, u8 reg, in i740outreg_mask() argument
[all …]
Dssd1307fb.c147 static void ssd1307fb_update_display(struct ssd1307fb_par *par) in ssd1307fb_update_display() argument
150 u8 *vmem = par->info->screen_base; in ssd1307fb_update_display()
153 array = ssd1307fb_alloc_array(par->width * par->height / 8, in ssd1307fb_update_display()
187 for (i = 0; i < (par->height / 8); i++) { in ssd1307fb_update_display()
188 for (j = 0; j < par->width; j++) { in ssd1307fb_update_display()
189 u32 array_idx = i * par->width + j; in ssd1307fb_update_display()
192 u32 page_length = par->width * i; in ssd1307fb_update_display()
193 u32 index = page_length + (par->width * k + j) / 8; in ssd1307fb_update_display()
202 ssd1307fb_write_array(par->client, array, par->width * par->height / 8); in ssd1307fb_update_display()
210 struct ssd1307fb_par *par = info->par; in ssd1307fb_write() local
[all …]
Ds3fb.c191 static u8 s3fb_ddc_read(struct s3fb_info *par) in s3fb_ddc_read() argument
193 if (s3fb_ddc_needs_mmio(par->chip)) in s3fb_ddc_read()
194 return readb(par->mmio + DDC_MMIO_REG); in s3fb_ddc_read()
196 return vga_rcrt(par->state.vgabase, DDC_REG); in s3fb_ddc_read()
199 static void s3fb_ddc_write(struct s3fb_info *par, u8 val) in s3fb_ddc_write() argument
201 if (s3fb_ddc_needs_mmio(par->chip)) in s3fb_ddc_write()
202 writeb(val, par->mmio + DDC_MMIO_REG); in s3fb_ddc_write()
204 vga_wcrt(par->state.vgabase, DDC_REG, val); in s3fb_ddc_write()
209 struct s3fb_info *par = data; in s3fb_ddc_setscl() local
212 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; in s3fb_ddc_setscl()
[all …]
Dtridentfb.c39 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
41 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
43 (struct tridentfb_par *par, const char*,
173 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v) in writemmr() argument
175 fb_writel(v, par->io_virt + r); in writemmr()
178 static inline u32 readmmr(struct tridentfb_par *par, u16 r) in readmmr() argument
180 return fb_readl(par->io_virt + r); in readmmr()
191 struct tridentfb_par *par = data; in tridentfb_ddc_setscl_tgui() local
192 u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI; in tridentfb_ddc_setscl_tgui()
199 vga_mm_wcrt(par->io_virt, I2C, reg); in tridentfb_ddc_setscl_tgui()
[all …]
/drivers/video/fbdev/geode/
Dsuspend_gx.c20 static void gx_save_regs(struct gxfb_par *par) in gx_save_regs() argument
26 i = read_gp(par, GP_BLT_STATUS); in gx_save_regs()
30 rdmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel); in gx_save_regs()
31 rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll); in gx_save_regs()
33 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); in gx_save_regs()
36 memcpy(par->gp, par->gp_regs, sizeof(par->gp)); in gx_save_regs()
37 memcpy(par->dc, par->dc_regs, sizeof(par->dc)); in gx_save_regs()
38 memcpy(par->vp, par->vid_regs, sizeof(par->vp)); in gx_save_regs()
39 memcpy(par->fp, par->vid_regs + VP_FP_START, sizeof(par->fp)); in gx_save_regs()
42 write_dc(par, DC_PAL_ADDRESS, 0); in gx_save_regs()
[all …]
Dlxfb_ops.c186 struct lxfb_par *par = info->par; in lx_graphics_disable() local
191 write_vp(par, VP_A1T, 0); in lx_graphics_disable()
192 write_vp(par, VP_A2T, 0); in lx_graphics_disable()
193 write_vp(par, VP_A3T, 0); in lx_graphics_disable()
196 val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE | in lx_graphics_disable()
199 write_dc(par, DC_GENERAL_CFG, val); in lx_graphics_disable()
201 val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN; in lx_graphics_disable()
202 write_vp(par, VP_VCFG, val); in lx_graphics_disable()
204 write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK | in lx_graphics_disable()
207 val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN; in lx_graphics_disable()
[all …]
/drivers/video/fbdev/riva/
Dnv_driver.c46 static inline unsigned char MISCin(struct riva_par *par) in MISCin() argument
48 return (VGA_RD08(par->riva.PVIO, 0x3cc)); in MISCin()
52 riva_is_connected(struct riva_par *par, Bool second) in riva_is_connected() argument
54 volatile U032 __iomem *PRAMDAC = par->riva.PRAMDAC0; in riva_is_connected()
69 NV_WR32(par->riva.PRAMDAC0, 0x0610, 0x94050140); in riva_is_connected()
70 NV_WR32(par->riva.PRAMDAC0, 0x0608, 0x00001000); in riva_is_connected()
76 NV_WR32(par->riva.PRAMDAC0, 0x0608, in riva_is_connected()
77 NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF); in riva_is_connected()
86 riva_override_CRTC(struct riva_par *par) in riva_override_CRTC() argument
90 par->SecondCRTC ? 1 : 0); in riva_override_CRTC()
[all …]
/drivers/video/fbdev/aty/
Datyfb_base.c149 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par) in aty_st_lcd() argument
152 aty_st_le32(lt_lcd_regs[index], val, par); in aty_st_lcd()
157 temp = aty_ld_le32(LCD_INDEX, par); in aty_st_lcd()
158 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par); in aty_st_lcd()
160 aty_st_le32(LCD_DATA, val, par); in aty_st_lcd()
164 u32 aty_ld_lcd(int index, const struct atyfb_par *par) in aty_ld_lcd() argument
167 return aty_ld_le32(lt_lcd_regs[index], par); in aty_ld_lcd()
172 temp = aty_ld_le32(LCD_INDEX, par); in aty_ld_lcd()
173 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par); in aty_ld_lcd()
175 return aty_ld_le32(LCD_DATA, par); in aty_ld_lcd()
[all …]

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