| /drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/ |
| D | phy_n.c | 36 #define READ_RADIO_REG2(pi, radio_type, jspace, core, reg_name) \ argument
37 read_radio_reg(pi, radio_type##_##jspace##_##reg_name | \
42 #define WRITE_RADIO_REG2(pi, radio_type, jspace, core, reg_name, value) \ argument
43 write_radio_reg(pi, radio_type##_##jspace##_##reg_name | \
48 #define WRITE_RADIO_SYN(pi, radio_type, reg_name, value) \ argument
49 write_radio_reg(pi, radio_type##_##SYN##_##reg_name, value)
51 #define READ_RADIO_REG3(pi, radio_type, jspace, core, reg_name) \ argument
52 read_radio_reg(pi, ((core == PHY_CORE_0) ? \
56 #define WRITE_RADIO_REG3(pi, radio_type, jspace, core, reg_name, value) \ argument
57 write_radio_reg(pi, ((core == PHY_CORE_0) ? \
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| D | phy_lcn.c | 90 #define wlc_lcnphy_enable_tx_gain_override(pi) \ argument
91 wlc_lcnphy_set_tx_gain_override(pi, true)
92 #define wlc_lcnphy_disable_tx_gain_override(pi) \ argument
93 wlc_lcnphy_set_tx_gain_override(pi, false)
95 #define wlc_lcnphy_iqcal_active(pi) \ argument
96 (read_phy_reg((pi), 0x451) & \
99 #define txpwrctrl_off(pi) (0x7 != ((read_phy_reg(pi, 0x4a4) & 0xE000) >> 13)) argument
100 #define wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) \ argument
101 (pi->temppwrctrl_capable)
102 #define wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) \ argument
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| D | phy_cmn.c | 37 #define VALID_RADIO(pi, radioid) ( \ argument
38 (ISNPHY(pi) ? VALID_N_RADIO(radioid) : false) || \
39 (ISLCNPHY(pi) ? VALID_LCN_RADIO(radioid) : false))
131 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro); in wlc_phyreg_enter() local
132 wlapi_bmac_ucode_wake_override_phyreg_set(pi->sh->physhim); in wlc_phyreg_enter()
137 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro); in wlc_phyreg_exit() local
138 wlapi_bmac_ucode_wake_override_phyreg_clear(pi->sh->physhim); in wlc_phyreg_exit()
143 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro); in wlc_radioreg_enter() local
144 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, MCTL_LOCK_RADIO); in wlc_radioreg_enter()
151 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro); in wlc_radioreg_exit() local
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| D | phy_int.h | 43 #define ISNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N) argument
44 #define ISLCNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN) argument
180 #define PHY_PERICAL_MPHASE_PENDING(pi) \ argument
181 (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE)
233 #define SCAN_INPROG_PHY(pi) \ argument
234 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN))
236 #define PLT_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT)) argument
238 #define ASSOC_INPROG_PHY(pi) \ argument
239 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC))
241 #define SCAN_RM_IN_PROGRESS(pi) \ argument
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| /drivers/block/paride/ |
| D | paride.c | 45 void pi_write_regr(PIA * pi, int cont, int regr, int val) in pi_write_regr() argument
47 pi->proto->write_regr(pi, cont, regr, val); in pi_write_regr()
52 int pi_read_regr(PIA * pi, int cont, int regr) in pi_read_regr() argument
54 return pi->proto->read_regr(pi, cont, regr); in pi_read_regr()
59 void pi_write_block(PIA * pi, char *buf, int count) in pi_write_block() argument
61 pi->proto->write_block(pi, buf, count); in pi_write_block()
66 void pi_read_block(PIA * pi, char *buf, int count) in pi_read_block() argument
68 pi->proto->read_block(pi, buf, count); in pi_read_block()
75 PIA *pi = (PIA *) p; in pi_wake_up() local
81 if (pi->claim_cont && !parport_claim(pi->pardev)) { in pi_wake_up()
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| D | bpck6.c | 40 #define PPCSTRUCT(pi) ((Interface *)(pi->private)) argument
59 static int bpck6_read_regr(PIA *pi, int cont, int reg) in bpck6_read_regr() argument
68 out=ppc6_rd_port(PPCSTRUCT(pi),cont?reg|8:reg); in bpck6_read_regr()
72 static void bpck6_write_regr(PIA *pi, int cont, int reg, int val) in bpck6_write_regr() argument
77 ppc6_wr_port(PPCSTRUCT(pi),cont?reg|8:reg,(u8)val); in bpck6_write_regr()
81 static void bpck6_write_block( PIA *pi, char * buf, int len ) in bpck6_write_block() argument
83 ppc6_wr_port16_blk(PPCSTRUCT(pi),ATAPI_DATA,buf,(u32)len>>1); in bpck6_write_block()
86 static void bpck6_read_block( PIA *pi, char * buf, int len ) in bpck6_read_block() argument
88 ppc6_rd_port16_blk(PPCSTRUCT(pi),ATAPI_DATA,buf,(u32)len>>1); in bpck6_read_block()
91 static void bpck6_connect ( PIA *pi ) in bpck6_connect() argument
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| D | frpw.c | 47 static int frpw_read_regr( PIA *pi, int cont, int regr ) in frpw_read_regr() argument
63 static void frpw_write_regr( PIA *pi, int cont, int regr, int val) in frpw_write_regr() argument
74 static void frpw_read_block_int( PIA *pi, char * buf, int count, int regr ) in frpw_read_block_int() argument
78 switch(pi->mode) { in frpw_read_block_int()
135 static void frpw_read_block( PIA *pi, char * buf, int count) in frpw_read_block() argument
137 { frpw_read_block_int(pi,buf,count,0x08); in frpw_read_block()
140 static void frpw_write_block( PIA *pi, char * buf, int count ) in frpw_write_block() argument
144 switch(pi->mode) { in frpw_write_block()
173 static void frpw_connect ( PIA *pi ) in frpw_connect() argument
175 { pi->saved_r0 = r0(); in frpw_connect()
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| D | bpck.c | 32 #define PC pi->private
48 static int bpck_read_regr( PIA *pi, int cont, int regr ) in bpck_read_regr() argument
54 switch (pi->mode) { in bpck_read_regr()
79 static void bpck_write_regr( PIA *pi, int cont, int regr, int val ) in bpck_write_regr() argument
85 switch (pi->mode) { in bpck_write_regr()
105 #define WR(r,v) bpck_write_regr(pi,2,r,v)
106 #define RR(r) (bpck_read_regr(pi,2,r))
108 static void bpck_write_block( PIA *pi, char * buf, int count ) in bpck_write_block() argument
112 switch (pi->mode) { in bpck_write_block()
149 static void bpck_read_block( PIA *pi, char * buf, int count ) in bpck_read_block() argument
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| D | friq.c | 51 static int friq_read_regr( PIA *pi, int cont, int regr ) in friq_read_regr() argument
66 static void friq_write_regr( PIA *pi, int cont, int regr, int val) in friq_write_regr() argument
77 static void friq_read_block_int( PIA *pi, char * buf, int count, int regr ) in friq_read_block_int() argument
81 switch(pi->mode) { in friq_read_block_int()
132 static void friq_read_block( PIA *pi, char * buf, int count) in friq_read_block() argument
134 { friq_read_block_int(pi,buf,count,0x08); in friq_read_block()
137 static void friq_write_block( PIA *pi, char * buf, int count ) in friq_write_block() argument
141 switch(pi->mode) { in friq_write_block()
169 static void friq_connect ( PIA *pi ) in friq_connect() argument
171 { pi->saved_r0 = r0(); in friq_connect()
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| D | on26.c | 47 static int on26_read_regr( PIA *pi, int cont, int regr ) in on26_read_regr() argument
53 switch (pi->mode) { in on26_read_regr()
76 static void on26_write_regr( PIA *pi, int cont, int regr, int val ) in on26_write_regr() argument
82 switch (pi->mode) { in on26_write_regr()
102 static void on26_connect ( PIA *pi ) in on26_connect() argument
106 pi->saved_r0 = r0(); in on26_connect()
107 pi->saved_r2 = r2(); in on26_connect()
110 x = 8; if (pi->mode) x = 9; in on26_connect()
116 static void on26_disconnect ( PIA *pi ) in on26_disconnect() argument
118 { if (pi->mode >= 2) { w3(4); w3(4); w3(4); w3(4); } in on26_disconnect()
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| D | pt.c | 218 struct pi_adapter *pi; member
252 static inline int status_reg(struct pi_adapter *pi) in status_reg() argument
254 return pi_read_regr(pi, 1, 6); in status_reg()
257 static inline int read_reg(struct pi_adapter *pi, int reg) in read_reg() argument
259 return pi_read_regr(pi, 0, reg); in read_reg()
262 static inline void write_reg(struct pi_adapter *pi, int reg, int val) in write_reg() argument
264 pi_write_regr(pi, 0, reg, val); in write_reg()
275 struct pi_adapter *pi = tape->pi; in pt_wait() local
278 while ((((r = status_reg(pi)) & go) || (stop && (!(r & stop)))) in pt_wait()
283 s = read_reg(pi, 7); in pt_wait()
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| D | epat.c | 47 static void epat_write_regr( PIA *pi, int cont, int regr, int val) in epat_write_regr() argument
53 switch (pi->mode) { in epat_write_regr()
68 static int epat_read_regr( PIA *pi, int cont, int regr ) in epat_read_regr() argument
74 switch (pi->mode) { in epat_read_regr()
97 static void epat_read_block( PIA *pi, char * buf, int count ) in epat_read_block() argument
101 switch (pi->mode) { in epat_read_block()
162 static void epat_write_block( PIA *pi, char * buf, int count ) in epat_write_block() argument
166 switch (pi->mode) { in epat_write_block()
200 #define WR(r,v) epat_write_regr(pi,2,r,v)
201 #define RR(r) (epat_read_regr(pi,2,r))
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| /drivers/tty/serial/ |
| D | mpsc.c | 317 static void mpsc_start_rx(struct mpsc_port_info *pi);
318 static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
327 static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src) in mpsc_brg_init() argument
331 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); in mpsc_brg_init()
334 if (pi->brg_can_tune) in mpsc_brg_init()
337 if (pi->mirror_regs) in mpsc_brg_init()
338 pi->BRG_BCR_m = v; in mpsc_brg_init()
339 writel(v, pi->brg_base + BRG_BCR); in mpsc_brg_init()
341 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000, in mpsc_brg_init()
342 pi->brg_base + BRG_BTR); in mpsc_brg_init()
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| /drivers/gpu/drm/radeon/ |
| D | kv_dpm.c | 251 struct kv_power_info *pi = rdev->pm.dpm.priv; in kv_get_pi() local
253 return pi; in kv_get_pi()
333 struct kv_power_info *pi = kv_get_pi(rdev); in kv_do_enable_didt() local
336 if (pi->caps_sq_ramping) { in kv_do_enable_didt()
345 if (pi->caps_db_ramping) { in kv_do_enable_didt()
354 if (pi->caps_td_ramping) { in kv_do_enable_didt()
363 if (pi->caps_tcp_ramping) { in kv_do_enable_didt()
375 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_didt() local
378 if (pi->caps_sq_ramping || in kv_enable_didt()
379 pi->caps_db_ramping || in kv_enable_didt()
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| D | ci_dpm.c | 195 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi() local
197 return pi; in ci_get_pi()
209 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_powertune_defaults() local
219 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
225 pi->powertune_defaults = &defaults_saturn_xt; in ci_initialize_powertune_defaults()
229 pi->powertune_defaults = &defaults_hawaii_xt; in ci_initialize_powertune_defaults()
233 pi->powertune_defaults = &defaults_hawaii_pro; in ci_initialize_powertune_defaults()
243 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
247 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
249 pi->caps_power_containment = true; in ci_initialize_powertune_defaults()
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| D | rv770_dpm.c | 57 struct rv7xx_power_info *pi = rdev->pm.dpm.priv; in rv770_get_pi() local
59 return pi; in rv770_get_pi()
64 struct evergreen_power_info *pi = rdev->pm.dpm.priv; in evergreen_get_pi() local
66 return pi; in evergreen_get_pi()
72 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in rv770_enable_bif_dynamic_pcie_gen2() local
81 if (!pi->boot_in_gen2) { in rv770_enable_bif_dynamic_pcie_gen2()
146 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in rv770_mg_clock_gating_enable() local
159 if (pi->mgcgtssm) in rv770_mg_clock_gating_enable()
238 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
241 pi->soft_regs_start + reg_offset,
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| D | rv6xx_dpm.c | 46 struct rv6xx_power_info *pi = rdev->pm.dpm.priv; in rv6xx_get_pi() local
48 return pi; in rv6xx_get_pi()
163 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_output_stepping() local
168 pi->spll_ref_div, in rv6xx_output_stepping()
184 fb_divider = ((step->vco_frequency * pi->spll_ref_div) / ref_clk) >> in rv6xx_output_stepping()
185 pi->fb_div_scale; in rv6xx_output_stepping()
188 pi->spll_ref_div - 1); in rv6xx_output_stepping()
437 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_calculate_engine_speed_stepping_parameters() local
439 pi->hw.sclks[R600_POWER_LEVEL_LOW] = in rv6xx_calculate_engine_speed_stepping_parameters()
441 pi->hw.sclks[R600_POWER_LEVEL_MEDIUM] = in rv6xx_calculate_engine_speed_stepping_parameters()
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| D | sumo_dpm.c | 84 struct sumo_power_info *pi = rdev->pm.dpm.priv; in sumo_get_pi() local
86 return pi; in sumo_get_pi()
287 struct sumo_power_info *pi = sumo_get_pi(rdev); in sumo_enable_clock_power_gating() local
289 if (pi->enable_gfx_clock_gating) in sumo_enable_clock_power_gating()
291 if (pi->enable_gfx_power_gating) in sumo_enable_clock_power_gating()
293 if (pi->enable_mg_clock_gating) in sumo_enable_clock_power_gating()
295 if (pi->enable_gfx_clock_gating) in sumo_enable_clock_power_gating()
297 if (pi->enable_gfx_power_gating) in sumo_enable_clock_power_gating()
305 struct sumo_power_info *pi = sumo_get_pi(rdev); in sumo_disable_clock_power_gating() local
307 if (pi->enable_gfx_clock_gating) in sumo_disable_clock_power_gating()
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| D | trinity_dpm.c | 356 struct trinity_power_info *pi = rdev->pm.dpm.priv; in trinity_get_pi() local
358 return pi; in trinity_get_pi()
363 struct trinity_power_info *pi = trinity_get_pi(rdev); in trinity_gfx_powergating_initialize() local
391 if (pi->override_dynamic_mgpg && (hw_rev == 0)) in trinity_gfx_powergating_initialize()
546 struct trinity_power_info *pi = trinity_get_pi(rdev); in trinity_enable_clock_power_gating() local
548 if (pi->enable_gfx_clock_gating) in trinity_enable_clock_power_gating()
550 if (pi->enable_mg_clock_gating) in trinity_enable_clock_power_gating()
552 if (pi->enable_gfx_power_gating) in trinity_enable_clock_power_gating()
554 if (pi->enable_mg_clock_gating) { in trinity_enable_clock_power_gating()
558 if (pi->enable_gfx_clock_gating) in trinity_enable_clock_power_gating()
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| D | rv730_dpm.c | 44 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in rv730_populate_sclk_value() local
46 u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl; in rv730_populate_sclk_value()
47 u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2; in rv730_populate_sclk_value()
48 u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3; in rv730_populate_sclk_value()
49 u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum; in rv730_populate_sclk_value()
50 u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2; in rv730_populate_sclk_value()
91 if (pi->sclk_ss) { in rv730_populate_sclk_value()
123 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in rv730_populate_mclk_value() local
124 u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl; in rv730_populate_mclk_value()
125 u32 dll_cntl = pi->clk_regs.rv730.dll_cntl; in rv730_populate_mclk_value()
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| D | rv740_dpm.c | 124 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in rv740_populate_sclk_value() local
126 u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; in rv740_populate_sclk_value()
127 u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2; in rv740_populate_sclk_value()
128 u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3; in rv740_populate_sclk_value()
129 u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum; in rv740_populate_sclk_value()
130 u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2; in rv740_populate_sclk_value()
159 if (pi->sclk_ss) { in rv740_populate_sclk_value()
191 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in rv740_populate_mclk_value() local
192 u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl; in rv740_populate_mclk_value()
193 u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2; in rv740_populate_mclk_value()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | kv_dpm.c | 381 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi() local
383 return pi; in kv_get_pi()
463 struct kv_power_info *pi = kv_get_pi(adev); in kv_do_enable_didt() local
466 if (pi->caps_sq_ramping) { in kv_do_enable_didt()
475 if (pi->caps_db_ramping) { in kv_do_enable_didt()
484 if (pi->caps_td_ramping) { in kv_do_enable_didt()
493 if (pi->caps_tcp_ramping) { in kv_do_enable_didt()
505 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_didt() local
508 if (pi->caps_sq_ramping || in kv_enable_didt()
509 pi->caps_db_ramping || in kv_enable_didt()
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| D | cz_dpm.c | 58 struct cz_power_info *pi = adev->pm.dpm.priv; in cz_get_pi() local
60 return pi; in cz_get_pi()
74 struct cz_power_info *pi = cz_get_pi(adev); in cz_construct_max_power_limits_table() local
84 table->mclk = pi->sys_info.nbp_memory_clock[0]; in cz_construct_max_power_limits_table()
97 struct cz_power_info *pi = cz_get_pi(adev); in cz_parse_sys_info_table() local
114 pi->sys_info.bootup_sclk = in cz_parse_sys_info_table()
116 pi->sys_info.bootup_uma_clk = in cz_parse_sys_info_table()
118 pi->sys_info.dentist_vco_freq = in cz_parse_sys_info_table()
120 pi->sys_info.bootup_nb_voltage_index = in cz_parse_sys_info_table()
124 pi->sys_info.htc_tmp_lmt = 203; in cz_parse_sys_info_table()
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| D | ci_dpm.c | 320 struct ci_power_info *pi = adev->pm.dpm.priv; in ci_get_pi() local
322 return pi; in ci_get_pi()
334 struct ci_power_info *pi = ci_get_pi(adev); in ci_initialize_powertune_defaults() local
344 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
350 pi->powertune_defaults = &defaults_saturn_xt; in ci_initialize_powertune_defaults()
354 pi->powertune_defaults = &defaults_hawaii_xt; in ci_initialize_powertune_defaults()
358 pi->powertune_defaults = &defaults_hawaii_pro; in ci_initialize_powertune_defaults()
368 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
372 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
374 pi->caps_power_containment = true; in ci_initialize_powertune_defaults()
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| /drivers/md/ |
| D | dm-queue-length.c | 68 struct path_info *pi, *next; in ql_free_paths() local
70 list_for_each_entry_safe(pi, next, paths, list) { in ql_free_paths()
71 list_del(&pi->list); in ql_free_paths()
72 kfree(pi); in ql_free_paths()
90 struct path_info *pi; in ql_status() local
96 pi = path->pscontext; in ql_status()
100 DMEMIT("%d ", atomic_read(&pi->qlen)); in ql_status()
103 DMEMIT("%u ", pi->repeat_count); in ql_status()
115 struct path_info *pi; in ql_add_path() local
141 pi = kmalloc(sizeof(*pi), GFP_KERNEL); in ql_add_path()
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