Searched refs:pll0 (Results 1 – 9 of 9) sorted by relevance
| /drivers/bcma/ |
| D | driver_chipcommon_pmu.c | 84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
349 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
354 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); in bcma_pmu_pll_clock()
366 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); in bcma_pmu_pll_clock()
370 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF); in bcma_pmu_pll_clock()
[all …]
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| /drivers/gpu/drm/tegra/ |
| D | hdmi.c | 32 u32 pll0; member
180 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
195 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
213 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
227 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
241 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
259 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
277 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
296 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
315 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
[all …]
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| /drivers/clk/mxs/ |
| D | clk-imx28.c | 139 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
174 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
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| /drivers/gpu/drm/i915/ |
| D | intel_dpll_mgr.h | 92 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, member
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| D | intel_dpll_mgr.c | 1394 temp |= pll->config.hw_state.pll0; in bxt_ddi_pll_enable()
1504 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); in bxt_ddi_pll_get_hw_state()
1505 hw_state->pll0 &= PORT_PLL_M2_MASK; in bxt_ddi_pll_get_hw_state()
1662 dpll_hw_state->pll0 = clk_div->m2_int; in bxt_ddi_set_dpll_hw_state()
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| D | intel_ddi.c | 998 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; in bxt_calc_pll_link()
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| D | intel_display.c | 12839 pipe_config->dpll_hw_state.pll0, in intel_dump_pipe_config()
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| /drivers/clk/qcom/ |
| D | gcc-mdm9615.c | 48 static struct clk_pll pll0 = { variable
1571 [PLL0] = &pll0.clkr,
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| D | gcc-ipq806x.c | 35 static struct clk_pll pll0 = { variable
2686 [PLL0] = &pll0.clkr,
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