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Searched refs:read_csr (Results 1 – 16 of 16) sorted by relevance

/drivers/infiniband/hw/hfi1/
Dfirmware.c274 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) in __read_8051_data()
286 *result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA); in __read_8051_data()
359 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) in write_8051()
843 status = (read_csr(dd, MISC_CFG_FW_CTRL) in run_rsa()
878 status = (read_csr(dd, MISC_CFG_FW_CTRL) in run_rsa()
926 reg = read_csr(dd, MISC_ERR_STATUS); in run_rsa()
956 u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); in get_firmware_state()
1103 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); in sbus_read()
1224 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); in sbus_request_slow()
1228 u64 counts = read_csr(dd, ASIC_STS_SBUS_COUNTERS); in sbus_request_slow()
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Dintr.c135 read_csr(dd, DC_DC8051_STS_REMOTE_GUID); in handle_linkup_change()
137 read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) & in handle_linkup_change()
140 read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) & in handle_linkup_change()
Dqsfp.c74 reg = read_csr(dd, target_oe); in hfi1_setsda()
87 (void)read_csr(dd, target_oe); in hfi1_setsda()
98 reg = read_csr(dd, target_oe); in hfi1_setscl()
111 (void)read_csr(dd, target_oe); in hfi1_setscl()
124 reg = read_csr(bus->controlling_dd, target_in); in hfi1_getsda()
138 reg = read_csr(bus->controlling_dd, target_in); in hfi1_getscl()
686 reg = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_IN : ASIC_QSFP1_IN); in qsfp_mod_present()
Dpcie.c203 dd->chip_rcv_array_count = read_csr(dd, RCV_ARRAY_CNT); in hfi1_pcie_ddinit()
895 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); in arm_gasket_logic()
925 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); in write_xmt_margin()
1058 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); in do_pcie_gen3_transition()
1264 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ in do_pcie_gen3_transition()
1266 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); in do_pcie_gen3_transition()
1323 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); in do_pcie_gen3_transition()
Dchip.c1266 u64 read_csr(const struct hfi1_devdata *dd, u32 offset) in read_csr() function
1293 ret = read_csr(dd, csr); in read_write_csr()
5587 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */ in handle_send_egress_err_info()
5588 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO); in handle_send_egress_err_info()
6246 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1); in handle_8051_request()
6362 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN); in lcb_shutdown()
6363 reg = read_csr(dd, DCC_CFG_RESET); in lcb_shutdown()
6367 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */ in lcb_shutdown()
6596 rcvctrl = read_csr(dd, RCV_CTRL); in adjust_rcvctrl()
6664 reg = read_csr(dd, CCE_STATUS); in wait_for_freeze_status()
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Deprom.c94 result[i] = (u32)read_csr(dd, ASIC_EEP_DATA); in read_page()
Dchip.h579 u64 read_csr(const struct hfi1_devdata *dd, u32 offset);
591 return read_csr(dd, offset0 + (0x100 * ctxt)); in read_kctxt_csr()
626 return read_csr(dd, offset0 + (0x1000 * ctxt)); in read_uctxt_csr()
Dpio.c70 sendctrl = read_csr(dd, SEND_CTRL); in __cm_reset()
94 reg = read_csr(dd, SEND_CTRL); in pio_send_control()
130 (void)read_csr(dd, SEND_CTRL); /* flush write */ in pio_send_control()
980 reg = read_csr(dd, sc->hw_context * 8 + in sc_wait_for_packet_egress()
1174 reg = read_csr(dd, SEND_PIO_INIT_CTXT); in pio_init_wait_progress()
Ddebugfs.c463 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); in asic_flags_read()
527 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); in asic_flags_write()
531 (void)read_csr(dd, ASIC_CFG_SCRATCH); in asic_flags_write()
Dsdma.c315 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS); in sdma_wait_for_packet_egress()
2060 csr = read_csr(sde->dd, reg); \
2071 csr = read_csr(sde->dd, reg + (8 * i)); \
Dmad.c1471 *val++ = read_csr(dd, SEND_SC2VLT0); in get_sc2vlt_tables()
1472 *val++ = read_csr(dd, SEND_SC2VLT1); in get_sc2vlt_tables()
1473 *val++ = read_csr(dd, SEND_SC2VLT2); in get_sc2vlt_tables()
1474 *val++ = read_csr(dd, SEND_SC2VLT3); in get_sc2vlt_tables()
3027 reg = read_csr(dd, RCV_ERR_INFO); in pma_get_opa_errorinfo()
/drivers/net/ethernet/amd/
Dpcnet32.c246 u16 (*read_csr) (unsigned long, int); member
383 .read_csr = pcnet32_wio_read_csr,
438 .read_csr = pcnet32_dwio_read_csr,
463 val = lp->a->read_csr(ioaddr, CSR3); in pcnet32_netif_start()
957 x = a->read_csr(ioaddr, CSR15) & 0xfffc; in pcnet32_loopback_test()
1015 x = a->read_csr(ioaddr, CSR15); in pcnet32_loopback_test()
1087 csr5 = a->read_csr(ioaddr, CSR5); in pcnet32_suspend()
1092 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { in pcnet32_suspend()
1359 val = lp->a->read_csr(ioaddr, CSR3); in pcnet32_poll()
1393 csr0 = a->read_csr(ioaddr, CSR0); in pcnet32_get_regs()
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/drivers/firewire/
Dcore.h90 u32 (*read_csr)(struct fw_card *card, int csr_offset); member
Dcore-transaction.c1118 *data = cpu_to_be32(card->driver->read_csr(card, reg)); in handle_registers()
Dcore-cdev.c1214 cycle_time = card->driver->read_csr(card, CSR_CYCLE_TIME); in ioctl_get_cycle_timer2()
Dohci.c3519 .read_csr = ohci_read_csr,