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Searched refs:refdiv (Results 1 – 13 of 13) sorted by relevance

/drivers/clk/rockchip/
Dclk-pll.c148 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) in rockchip_rk3036_pll_get_params()
170 do_div(rate64, cur.refdiv); in rockchip_rk3036_pll_recalc_rate()
176 do_div(frac_rate64, cur.refdiv); in rockchip_rk3036_pll_recalc_rate()
198 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
217 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, in rockchip_rk3036_pll_set_params()
314 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, in rockchip_rk3036_pll_init()
317 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
321 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3036_pll_init()
618 rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT) in rockchip_rk3399_pll_get_params()
644 do_div(rate64, cur.refdiv); in rockchip_rk3399_pll_recalc_rate()
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Dclk.h127 .refdiv = _refdiv, \
176 unsigned int refdiv; member
/drivers/clk/pistachio/
Dclk-pll.c209 if (!params || !params->refdiv) in pll_gf40lp_frac_set_rate()
215 vco = div64_u64(vco, params->refdiv << 24); in pll_gf40lp_frac_set_rate()
221 val = div64_u64(params->fref, params->refdiv); in pll_gf40lp_frac_set_rate()
232 val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | in pll_gf40lp_frac_set_rate()
366 if (!params || !params->refdiv) in pll_gf40lp_laint_set_rate()
369 vco = div_u64(params->fref * params->fbdiv, params->refdiv); in pll_gf40lp_laint_set_rate()
374 val = div_u64(params->fref, params->refdiv); in pll_gf40lp_laint_set_rate()
400 val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | in pll_gf40lp_laint_set_rate()
Dclk.h100 unsigned long long refdiv; member
/drivers/clk/berlin/
Dberlin2-avpll.c170 u32 reg, refdiv, fbdiv; in berlin2_avpll_vco_recalc_rate() local
175 refdiv = (reg & VCO_REFDIV_MASK) >> VCO_REFDIV_SHIFT; in berlin2_avpll_vco_recalc_rate()
176 refdiv = vco_refdiv[refdiv]; in berlin2_avpll_vco_recalc_rate()
179 do_div(freq, refdiv); in berlin2_avpll_vco_recalc_rate()
/drivers/media/dvb-frontends/
Dcx24113.c99 u8 refdiv; member
295 static u8 cx24113_set_ref_div(struct cx24113_state *state, u8 refdiv) in cx24113_set_ref_div() argument
298 refdiv = 2; in cx24113_set_ref_div()
299 return state->refdiv = refdiv; in cx24113_set_ref_div()
410 cx24113_set_nfr(state, n, f, state->refdiv); in cx24113_set_frequency()
/drivers/clk/
Dclk-axm5516.c55 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
61 refdiv = ((control >> 16) & 0x1f) + 1; in axxia_pllclk_recalc()
62 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
/drivers/net/wireless/ath/ath9k/
Dhw.c818 u32 regval, pll2_divint, pll2_divfrac, refdiv; in ath9k_hw_init_pll() local
831 refdiv = 1; in ath9k_hw_init_pll()
835 refdiv = 3; in ath9k_hw_init_pll()
841 refdiv = 5; in ath9k_hw_init_pll()
847 refdiv = 1; in ath9k_hw_init_pll()
859 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | in ath9k_hw_init_pll()
/drivers/gpu/drm/amd/amdgpu/
Datombios_crtc.c339 if (amdgpu_crtc->ss.refdiv) { in amdgpu_atombios_crtc_adjust_pll()
341 amdgpu_crtc->pll_reference_div = amdgpu_crtc->ss.refdiv; in amdgpu_atombios_crtc_adjust_pll()
Damdgpu_mode.h366 uint8_t refdiv; member
/drivers/gpu/drm/radeon/
Dradeon_mode.h315 uint8_t refdiv; member
Datombios_crtc.c627 if (radeon_crtc->ss.refdiv) { in atombios_adjust_pll()
629 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; in atombios_adjust_pll()
Dradeon_atombios.c1416 ss->refdiv = ss_assign->ucRecommendedRef_Div; in radeon_atombios_get_ppll_ss_info()