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Searched refs:reg_block (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/powerplay/hwmgr/
Dppatomctrl.c48 ATOM_INIT_REG_BLOCK *reg_block, in atomctrl_retrieve_ac_timing() argument
54 ((uint8_t *)reg_block + (2 * sizeof(uint16_t)) + le16_to_cpu(reg_block->usRegIndexTblSize)); in atomctrl_retrieve_ac_timing()
83 ((uint8_t *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)) ; in atomctrl_retrieve_ac_timing()
101 ATOM_INIT_REG_BLOCK *reg_block, in atomctrl_set_mc_reg_address_table() argument
105 uint8_t num_entries = (uint8_t)((le16_to_cpu(reg_block->usRegIndexTblSize)) in atomctrl_set_mc_reg_address_table()
107 ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0]; in atomctrl_set_mc_reg_address_table()
138 ATOM_INIT_REG_BLOCK *reg_block; in atomctrl_initialize_mc_reg_table() local
156 reg_block = (ATOM_INIT_REG_BLOCK *) in atomctrl_initialize_mc_reg_table()
158 result = atomctrl_set_mc_reg_address_table(reg_block, table); in atomctrl_initialize_mc_reg_table()
163 reg_block, table); in atomctrl_initialize_mc_reg_table()
/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c3089 u32 reg_block, lb_interrupt_mask; in dce_v8_0_set_crtc_vblank_interrupt_state() local
3098 reg_block = CRTC0_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()
3101 reg_block = CRTC1_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()
3104 reg_block = CRTC2_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()
3107 reg_block = CRTC3_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()
3110 reg_block = CRTC4_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()
3113 reg_block = CRTC5_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()
3122 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); in dce_v8_0_set_crtc_vblank_interrupt_state()
3124 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); in dce_v8_0_set_crtc_vblank_interrupt_state()
3127 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); in dce_v8_0_set_crtc_vblank_interrupt_state()
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Datom.c187 idx += gctx->reg_block; in atom_get_src_int()
257 val = gctx->reg_block; in atom_get_src_int()
462 idx += gctx->reg_block; in atom_put_dst()
527 gctx->reg_block = val; in atom_put_dst()
916 ctx->ctx->reg_block = U16(*ptr); in atom_op_setregblock()
918 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); in atom_op_setregblock()
1274 ctx->reg_block = 0; in amdgpu_atom_execute_table()
Ddce_v6_0.c2523 u32 reg_block, interrupt_mask; in dce_v6_0_set_crtc_vblank_interrupt_state() local
2532 reg_block = SI_CRTC0_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
2535 reg_block = SI_CRTC1_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
2538 reg_block = SI_CRTC2_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
2541 reg_block = SI_CRTC3_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
2544 reg_block = SI_CRTC4_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
2547 reg_block = SI_CRTC5_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
2556 interrupt_mask = RREG32(INT_MASK + reg_block); in dce_v6_0_set_crtc_vblank_interrupt_state()
2558 WREG32(INT_MASK + reg_block, interrupt_mask); in dce_v6_0_set_crtc_vblank_interrupt_state()
2561 interrupt_mask = RREG32(INT_MASK + reg_block); in dce_v6_0_set_crtc_vblank_interrupt_state()
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Datom.h136 uint16_t reg_block; member
Damdgpu_atombios.c1658 ATOM_INIT_REG_BLOCK *reg_block = in amdgpu_atombios_init_mc_reg_table() local
1663 ((u8 *)reg_block + (2 * sizeof(u16)) + in amdgpu_atombios_init_mc_reg_table()
1664 le16_to_cpu(reg_block->usRegIndexTblSize)); in amdgpu_atombios_init_mc_reg_table()
1665 ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0]; in amdgpu_atombios_init_mc_reg_table()
1666 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / in amdgpu_atombios_init_mc_reg_table()
1703 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); in amdgpu_atombios_init_mc_reg_table()
/drivers/gpu/drm/radeon/
Datom.c191 idx += gctx->reg_block; in atom_get_src_int()
261 val = gctx->reg_block; in atom_get_src_int()
466 idx += gctx->reg_block; in atom_put_dst()
531 gctx->reg_block = val; in atom_put_dst()
885 ctx->ctx->reg_block = U16(*ptr); in atom_op_setregblock()
887 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); in atom_op_setregblock()
1229 ctx->reg_block = 0; in atom_execute_table_scratch_unlocked()
Datom.h137 uint16_t reg_block; member
Dradeon_atombios.c3996 ATOM_INIT_REG_BLOCK *reg_block = in radeon_atom_init_mc_reg_table() local
4001 ((u8 *)reg_block + (2 * sizeof(u16)) + in radeon_atom_init_mc_reg_table()
4002 le16_to_cpu(reg_block->usRegIndexTblSize)); in radeon_atom_init_mc_reg_table()
4003 ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0]; in radeon_atom_init_mc_reg_table()
4004 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / in radeon_atom_init_mc_reg_table()
4041 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); in radeon_atom_init_mc_reg_table()
/drivers/net/ethernet/intel/i40e/
Di40e_common.c1065 u32 reg_block = 0; in i40e_pre_tx_queue_cfg() local
1069 reg_block = abs_queue_idx / 128; in i40e_pre_tx_queue_cfg()
1073 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); in i40e_pre_tx_queue_cfg()
1082 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); in i40e_pre_tx_queue_cfg()
1374 u32 reg_block = 0; in i40e_clear_hw() local
1377 reg_block = abs_queue_idx / 128; in i40e_clear_hw()
1381 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); in i40e_clear_hw()
1386 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); in i40e_clear_hw()